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[Qemu-devel] [PATCH v5 13/19] tcg-arm: Cleanup multiply subroutines
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v5 13/19] tcg-arm: Cleanup multiply subroutines |
Date: |
Sun, 31 Mar 2013 15:34:59 -0700 |
Make the code more readable by only having one copy of the magic
numbers, swapping registers as needed prior to that. Speed the
compiler by not applying the rd == rn avoidance for v6 or later.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/arm/tcg-target.c | 85 +++++++++++++++++++++++++++-------------------------
1 file changed, 45 insertions(+), 40 deletions(-)
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 6e1a4b5..24a2354 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -542,55 +542,60 @@ static void tcg_out_dat_rIN(TCGContext *s, int cond, int
opc, int opneg,
}
}
-static inline void tcg_out_mul32(TCGContext *s,
- int cond, int rd, int rs, int rm)
-{
- if (rd != rm)
- tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
- (rs << 8) | 0x90 | rm);
- else if (rd != rs)
- tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
- (rm << 8) | 0x90 | rs);
- else {
- tcg_out32(s, (cond << 28) | (TCG_REG_TMP << 16) | (0 << 12) |
- (rs << 8) | 0x90 | rm);
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- rd, 0, TCG_REG_TMP, SHIFT_IMM_LSL(0));
+static inline void tcg_out_mul32(TCGContext *s, int cond, TCGReg rd,
+ TCGReg rn, TCGReg rm)
+{
+ /* if ArchVersion() < 6 && d == n then UNPREDICTABLE; */
+ if (!use_armv6_instructions && rd == rn) {
+ if (rd == rm) {
+ /* rd == rn == rm; copy an input to tmp first. */
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rm = rn = TCG_REG_TMP;
+ } else {
+ rn = rm;
+ rm = rd;
+ }
}
+ /* mul */
+ tcg_out32(s, (cond << 28) | 0x90 | (rd << 16) | (rm << 8) | rn);
}
-static inline void tcg_out_umull32(TCGContext *s,
- int cond, int rd0, int rd1, int rs, int rm)
+static inline void tcg_out_umull32(TCGContext *s, int cond, TCGReg rd0,
+ TCGReg rd1, TCGReg rn, TCGReg rm)
{
- if (rd0 != rm && rd1 != rm)
- tcg_out32(s, (cond << 28) | 0x800090 |
- (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
- else if (rd0 != rs && rd1 != rs)
- tcg_out32(s, (cond << 28) | 0x800090 |
- (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
- else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rm, SHIFT_IMM_LSL(0));
- tcg_out32(s, (cond << 28) | 0x800090 | TCG_REG_TMP |
- (rd1 << 16) | (rd0 << 12) | (rs << 8));
+ /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
+ if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
+ if (rd0 == rm || rd1 == rm) {
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rn = TCG_REG_TMP;
+ } else {
+ TCGReg t = rn;
+ rn = rm;
+ rm = t;
+ }
}
+ /* umull */
+ tcg_out32(s, (cond << 28) | 0x00800090 |
+ (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
}
-static inline void tcg_out_smull32(TCGContext *s,
- int cond, int rd0, int rd1, int rs, int rm)
+static inline void tcg_out_smull32(TCGContext *s, int cond, TCGReg rd0,
+ TCGReg rd1, TCGReg rn, TCGReg rm)
{
- if (rd0 != rm && rd1 != rm)
- tcg_out32(s, (cond << 28) | 0xc00090 |
- (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
- else if (rd0 != rs && rd1 != rs)
- tcg_out32(s, (cond << 28) | 0xc00090 |
- (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
- else {
- tcg_out_dat_reg(s, cond, ARITH_MOV,
- TCG_REG_TMP, 0, rm, SHIFT_IMM_LSL(0));
- tcg_out32(s, (cond << 28) | 0xc00090 | TCG_REG_TMP |
- (rd1 << 16) | (rd0 << 12) | (rs << 8));
+ /* if ArchVersion() < 6 && (dHi == n || dLo == n) then UNPREDICTABLE; */
+ if (!use_armv6_instructions && (rd0 == rn || rd1 == rn)) {
+ if (rd0 == rm || rd1 == rm) {
+ tcg_out_mov_reg(s, cond, TCG_REG_TMP, rn);
+ rn = TCG_REG_TMP;
+ } else {
+ TCGReg t = rn;
+ rn = rm;
+ rm = t;
+ }
}
+ /* smull */
+ tcg_out32(s, (cond << 28) | 0x00c00090 |
+ (rd1 << 16) | (rd0 << 12) | (rm << 8) | rn);
}
static inline void tcg_out_sdiv(TCGContext *s, int cond, int rd, int rn, int
rm)
--
1.8.1.4
- [Qemu-devel] [PATCH v5 04/19] tcg-arm: Handle negated constant arguments to and/sub, (continued)
- [Qemu-devel] [PATCH v5 04/19] tcg-arm: Handle negated constant arguments to and/sub, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 03/19] tcg-arm: Use bic to implement and with constant, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 05/19] tcg-arm: Allow constant first argument to sub, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 06/19] tcg-arm: Use tcg_out_dat_rIN for compares, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 08/19] tcg-arm: Improve constant generation, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 07/19] tcg-arm: Handle constant arguments to add2/sub2, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 09/19] tcg-arm: Implement deposit for armv7, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 10/19] tcg-arm: Implement division instructions, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 12/19] tcg-arm: Use R12 for the tcg temporary, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 11/19] tcg-arm: Use TCG_REG_TMP name for the tcg temporary, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 13/19] tcg-arm: Cleanup multiply subroutines,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 15/19] tcg-arm: Split out tcg_out_tlb_read, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 17/19] tcg-arm: Use movi32 + blx for calls on v7, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 14/19] tcg-arm: Cleanup most primitive load store subroutines, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 16/19] tcg-arm: Improve scheduling of tcg_out_tlb_read, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 18/19] tcg-arm: Convert to CONFIG_QEMU_LDST_OPTIMIZATION, Richard Henderson, 2013/03/31
- [Qemu-devel] [PATCH v5 19/19] tcg-arm: Tidy exit_tb, Richard Henderson, 2013/03/31