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Re: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high tran
From: |
Laszlo Ersek |
Subject: |
Re: [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition |
Date: |
Tue, 05 Mar 2013 19:05:52 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130216 Thunderbird/17.0.3 |
On 03/05/13 16:04, Paolo Bonzini wrote:
> The PIIX datasheet says that "before another INIT pulse can be
> generated via [port 92h], [bit 0] must be written back to a
> zero.
>
> This bug is masked right now because a full reset will clear the
> value of port 92h. But once we implement soft reset correctly,
> the next attempt to enable the A20 line by setting bit 1 (and
> leaving the others untouched) will cause another reset.
>
> Signed-off-by: Paolo Bonzini <address@hidden>
> ---
> hw/pc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/pc.c b/hw/pc.c
> index 07caba7..523db1f 100644
> --- a/hw/pc.c
> +++ b/hw/pc.c
> @@ -435,11 +435,12 @@ static void port92_write(void *opaque, hwaddr addr,
> uint64_t val,
> unsigned size)
> {
> Port92State *s = opaque;
> + int oldval = s->outport;
>
> DPRINTF("port92: write 0x%02x\n", val);
> s->outport = val;
> qemu_set_irq(*s->a20_out, (val >> 1) & 1);
> - if (val & 1) {
> + if ((val & 1) && !(oldval & 1)) {
> qemu_system_reset_request();
> }
> }
>
Reviewed-by: Laszlo Ersek <address@hidden>
- [Qemu-devel] [PATCH 0/3] Implement x86 soft reset, Paolo Bonzini, 2013/03/05
- [Qemu-devel] [PATCH 2/3] pc: port 92 reset requires a low->high transition, Paolo Bonzini, 2013/03/05
- [Qemu-devel] [PATCH 3/3] hw: correctly implement soft reset, Paolo Bonzini, 2013/03/05
- Re: [Qemu-devel] [PATCH 0/3] Implement x86 soft reset, David Woodhouse, 2013/03/05
- [Qemu-devel] [PATCH 4/3] wakeup: only reset the CPU, Paolo Bonzini, 2013/03/05