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Re: [Qemu-devel] [PATCH ppc-next v2 44/52] target-ppc: Set instruction f
From: |
Alexander Graf |
Subject: |
Re: [Qemu-devel] [PATCH ppc-next v2 44/52] target-ppc: Set instruction flags on CPU family classes |
Date: |
Fri, 22 Feb 2013 15:34:56 +0100 |
On 18.02.2013, at 10:16, Andreas Färber wrote:
> Signed-off-by: Andreas Färber <address@hidden>
> ---
> target-ppc/translate_init.c | 994 ++++++++++++++++++++++---------------------
> 1 Datei geändert, 499 Zeilen hinzugefügt(+), 495 Zeilen entfernt(-)
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 6043cf9..9fb9d1a 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -3275,13 +3275,6 @@ static int check_pow_hid0_74xx (CPUPPCState *env)
> static void glue(glue(ppc_, _name), _cpu_family_class_init)
>
> /* PowerPC 401
> */
> -#define POWERPC_INSNS_401 (PPC_INSNS_BASE | PPC_STRING |
> \
> - PPC_WRTEE | PPC_DCR |
> \
> - PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
> \
> - PPC_CACHE_DCBZ |
> \
> - PPC_MEM_SYNC | PPC_MEM_EIEIO |
> \
> - PPC_4xx_COMMON | PPC_40x_EXCP)
> -#define POWERPC_INSNS2_401 (PPC_NONE)
> #define POWERPC_MSRM_401 (0x00000000000FD201ULL)
> #define POWERPC_MMU_401 (POWERPC_MMU_REAL)
> #define POWERPC_EXCP_401 (POWERPC_EXCP_40x)
> @@ -3311,17 +3304,16 @@ POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
>
> pcc->init_proc = init_proc_401;
> pcc->check_pow = check_pow_nocheck;
> + pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
> + PPC_WRTEE | PPC_DCR |
> + PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
> + PPC_CACHE_DCBZ |
> + PPC_MEM_SYNC | PPC_MEM_EIEIO |
> + PPC_4xx_COMMON | PPC_40x_EXCP;
> + pcc->insns_flags2 = PPC_NONE;
The class is 0-initialized by default, right? So we can drop the insn_flags2 =
PPC_NONE bits. They were only here to make assignments happy.
This can easily be a follow-up patch though.
Alex
- [Qemu-devel] [PATCH ppc-next v2 36/52] target-ppc: Extract MPC5200/MPC5200B aliases, (continued)
- [Qemu-devel] [PATCH ppc-next v2 36/52] target-ppc: Extract MPC5200/MPC5200B aliases, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 45/52] target-ppc: Register all types for TARGET_PPCEMB, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 47/52] target-ppc: Turn descriptive CPU family comments into device descriptions, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 49/52] target-ppc: Update Coding Style for CPU models, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 39/52] target-ppc: Extract 970 aliases, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 38/52] target-ppc: Extract 405GPe alias, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 34/52] target-ppc: Extract MPC82xx_HiP{3, 4} aliases, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 50/52] target-ppc: Split model definitions out of translate_init.c, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 28/52] target-ppc: Extract MPC83xx aliases, Andreas Färber, 2013/02/18
- [Qemu-devel] [PATCH ppc-next v2 44/52] target-ppc: Set instruction flags on CPU family classes, Andreas Färber, 2013/02/18
- Re: [Qemu-devel] [PATCH ppc-next v2 44/52] target-ppc: Set instruction flags on CPU family classes,
Alexander Graf <=
[Qemu-devel] [PATCH ppc-next v2 40/52] target-ppc: Extract POWER7 alias, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 52/52] target-ppc: Change "POWER7" CPU alias, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 27/52] target-ppc: Extract e500v1/e500v2 aliases, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 43/52] target-ppc: Introduce abstract CPU family types, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 37/52] target-ppc: Extract MPC8240 alias, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 33/52] target-ppc: Extract MPC82xx aliases to *_HiP4, Andreas Färber, 2013/02/18
[Qemu-devel] [PATCH ppc-next v2 51/52] target-ppc: Fix remaining microcontroller typos among models, Andreas Färber, 2013/02/18