[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 38/38] target-xtensa: Use add2/sub2 for mac
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 38/38] target-xtensa: Use add2/sub2 for mac |
Date: |
Tue, 19 Feb 2013 23:52:26 -0800 |
Cc: Max Filippov <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-xtensa/translate.c | 29 +++++++++++++----------------
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index b41d12c..11e06a3 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2487,27 +2487,24 @@ static void disas_xtensa_insn(CPUXtensaState *env,
DisasContext *dc)
tcg_gen_sari_i32(cpu_SR[ACCHI], cpu_SR[ACCLO], 31);
}
} else {
- TCGv_i32 res = tcg_temp_new_i32();
- TCGv_i64 res64 = tcg_temp_new_i64();
- TCGv_i64 tmp = tcg_temp_new_i64();
-
- tcg_gen_mul_i32(res, m1, m2);
- tcg_gen_ext_i32_i64(res64, res);
- tcg_gen_concat_i32_i64(tmp,
- cpu_SR[ACCLO], cpu_SR[ACCHI]);
+ TCGv_i32 lo = tcg_temp_new_i32();
+ TCGv_i32 hi = tcg_temp_new_i32();
+
+ tcg_gen_mul_i32(lo, m1, m2);
+ tcg_gen_sari_i32(hi, lo, 31);
if (op == MAC16_MULA) {
- tcg_gen_add_i64(tmp, tmp, res64);
+ tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+ cpu_SR[ACCLO], cpu_SR[ACCHI],
+ lo, hi);
} else {
- tcg_gen_sub_i64(tmp, tmp, res64);
+ tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI],
+ cpu_SR[ACCLO], cpu_SR[ACCHI],
+ lo, hi);
}
- tcg_gen_trunc_i64_i32(cpu_SR[ACCLO], tmp);
- tcg_gen_shri_i64(tmp, tmp, 32);
- tcg_gen_trunc_i64_i32(cpu_SR[ACCHI], tmp);
tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]);
- tcg_temp_free(res);
- tcg_temp_free_i64(res64);
- tcg_temp_free_i64(tmp);
+ tcg_temp_free_i32(lo);
+ tcg_temp_free_i32(hi);
}
tcg_temp_free(m1);
tcg_temp_free(m2);
--
1.8.1.2
- [Qemu-devel] [PATCH 37/38] target-xtensa: Use mul*2 for mul*hi, (continued)
- [Qemu-devel] [PATCH 37/38] target-xtensa: Use mul*2 for mul*hi, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 35/38] target-sh4: Use mul*2 for dmul*, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 31/38] target-ppc: Compute arithmetic shift carry without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 29/38] target-ppc: Use add2 for carry generation, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 19/38] target-arm: Use add2 in gen_add_CC, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 27/38] target-ppc: Compute addition overflow without branches, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 22/38] target-mips: Use mul[us]2 in [D]MULT[U] insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 23/38] target-cris: Use mul*2 in mul* insns, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 25/38] target-ppc: Split out SO, OV, CA fields from XER, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 17/38] target-arm: Use mul[us]2 in gen_mul[us]_i64_i32, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 38/38] target-xtensa: Use add2/sub2 for mac,
Richard Henderson <=
- [Qemu-devel] [PATCH 26/38] target-ppc: Use setcond in gen_op_cmp, Richard Henderson, 2013/02/20
- [Qemu-devel] [PATCH 21/38] target-arm: Implement sbc_cc inline, Richard Henderson, 2013/02/20
- Re: [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Blue Swirl, 2013/02/23
- Re: [Qemu-devel] [PATCH 00/38] Add double-word addition and widening multiply tcg ops, Alexander Graf, 2013/02/25