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[Qemu-devel] [PATCH 24/57] target-i386: change gen_setcc_slow_T0 to gen_
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 24/57] target-i386: change gen_setcc_slow_T0 to gen_setcc_slow |
Date: |
Tue, 19 Feb 2013 09:39:58 -0800 |
From: Paolo Bonzini <address@hidden>
Do not hard code the destination register.
Reviewed-by: Blue Swirl <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 39 ++++++++++++++++++++-------------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ea1b003..c510732 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -1043,53 +1043,54 @@ static void gen_compute_eflags_z(DisasContext *s, TCGv
reg, bool inv)
}
}
-static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op, bool inv)
+static void gen_setcc_slow(DisasContext *s, int jcc_op, TCGv reg, bool inv)
{
+ assert(!TCGV_EQUAL(reg, cpu_cc_src));
switch(jcc_op) {
case JCC_O:
- gen_compute_eflags_o(s, cpu_T[0]);
+ gen_compute_eflags_o(s, reg);
break;
case JCC_B:
- gen_compute_eflags_c(s, cpu_T[0], inv);
+ gen_compute_eflags_c(s, reg, inv);
inv = false;
break;
case JCC_Z:
- gen_compute_eflags_z(s, cpu_T[0], inv);
+ gen_compute_eflags_z(s, reg, inv);
inv = false;
break;
case JCC_BE:
gen_compute_eflags(s);
- tcg_gen_shri_tl(cpu_T[0], cpu_cc_src, 6);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_cc_src);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
+ tcg_gen_shri_tl(reg, cpu_cc_src, 6);
+ tcg_gen_or_tl(reg, reg, cpu_cc_src);
+ tcg_gen_andi_tl(reg, reg, 1);
break;
case JCC_S:
- gen_compute_eflags_s(s, cpu_T[0], inv);
+ gen_compute_eflags_s(s, reg, inv);
inv = false;
break;
case JCC_P:
- gen_compute_eflags_p(s, cpu_T[0]);
+ gen_compute_eflags_p(s, reg);
break;
case JCC_L:
gen_compute_eflags(s);
- tcg_gen_shri_tl(cpu_T[0], cpu_cc_src, 11); /* CC_O */
+ tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 7); /* CC_S */
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
+ tcg_gen_xor_tl(reg, reg, cpu_tmp0);
+ tcg_gen_andi_tl(reg, reg, 1);
break;
default:
case JCC_LE:
gen_compute_eflags(s);
- tcg_gen_shri_tl(cpu_T[0], cpu_cc_src, 11); /* CC_O */
+ tcg_gen_shri_tl(reg, cpu_cc_src, 11); /* CC_O */
tcg_gen_shri_tl(cpu_tmp4, cpu_cc_src, 7); /* CC_S */
tcg_gen_shri_tl(cpu_tmp0, cpu_cc_src, 6); /* CC_Z */
- tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
- tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
- tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
+ tcg_gen_xor_tl(reg, reg, cpu_tmp4);
+ tcg_gen_or_tl(reg, reg, cpu_tmp0);
+ tcg_gen_andi_tl(reg, reg, 1);
break;
}
if (inv) {
- tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
+ tcg_gen_xori_tl(reg, reg, 1);
}
}
@@ -1256,7 +1257,7 @@ static inline void gen_jcc1(DisasContext *s, int b, int
l1)
break;
default:
slow_jcc:
- gen_setcc_slow_T0(s, jcc_op, false);
+ gen_setcc_slow(s, jcc_op, cpu_T[0], false);
tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
cpu_T[0], 0, l1);
break;
@@ -2510,7 +2511,7 @@ static void gen_setcc(DisasContext *s, int b)
worth to */
inv = b & 1;
jcc_op = (b >> 1) & 7;
- gen_setcc_slow_T0(s, jcc_op, inv);
+ gen_setcc_slow(s, jcc_op, cpu_T[0], inv);
}
}
--
1.8.1.2
- [Qemu-devel] [PATCH 01/57] test-i386: QEMU_PACKED is not defined here, (continued)
- [Qemu-devel] [PATCH 01/57] test-i386: QEMU_PACKED is not defined here, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 05/57] target-i386: factor setting of s->cc_op handling for string functions, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 03/57] target-i386: use OT_* consistently, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 04/57] target-i386: introduce gen_ext_tl, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 16/57] target-i386: Use gen_update_cc_op everywhere, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 17/57] target-i386: add helper functions to get other flags, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 23/57] target-i386: convert gen_compute_eflags_c to TCG, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 18/57] target-i386: do not compute eflags multiple times consecutively, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 25/57] target-i386: optimize setbe, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 24/57] target-i386: change gen_setcc_slow_T0 to gen_setcc_slow,
Richard Henderson <=
- [Qemu-devel] [PATCH 26/57] target-i386: optimize setle, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 22/57] target-i386: use inverted setcond when computing NS or NZ, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 38/57] target-i386: Update cc_op before TCG branches, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 56/57] target-i386: Implement tzcnt and fix lzcnt, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 52/57] target-i386: Implement SHLX, SARX, SHRX, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 36/57] target-i386: use gen_op for cmps/scas, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 41/57] target-i386: Make helper_cc_compute_{all, c} const, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 49/57] target-i386: Implement BZHI, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 37/57] target-i386: introduce gen_jcc1_noeob, Richard Henderson, 2013/02/19