[Qemu-devel] [PATCH v3 08/20] arm: add Faraday FTPWMTMR010 timer support

[Kuo-Jung Su]

From: Kuo-Jung Su <address@hidden>

The FTPWMTMR010 is an APB device which provides up to 8 independent timers.

Signed-off-by: Kuo-Jung Su <address@hidden>
---
 hw/arm/Makefile.objs  |    1 +
 hw/arm/faraday_a369.c |   11 +++
 hw/arm/ftpwmtmr010.c  |  246 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/arm/ftpwmtmr010.h  |   25 +++++
 4 files changed, 283 insertions(+)
 create mode 100644 hw/arm/ftpwmtmr010.c
 create mode 100644 hw/arm/ftpwmtmr010.h

diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 2f34229..04904e7 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -39,4 +39,5 @@ obj-y += ftahbc020.o
 obj-y += ftddrii030.o
 obj-y += ftintc020.o
 obj-y += fttmr010.o
+obj-y += ftpwmtmr010.o
 obj-y += ftwdt010.o
diff --git a/hw/arm/faraday_a369.c b/hw/arm/faraday_a369.c
index 1cc7661..89911e3 100644
--- a/hw/arm/faraday_a369.c
+++ b/hw/arm/faraday_a369.c
@@ -41,10 +41,21 @@ static void
 a369_device_init(A369State *s)
 {
     qemu_irq *pic;
+    DeviceState *ds;
 
     /* Interrupt Controller */
     pic = ftintc020_init(0x90100000, s->cpu);
 
+    /* Timer */
+    ds = qdev_create(NULL, "ftpwmtmr010");
+    qdev_prop_set_uint32(ds, "freq", 66 * 1000000);
+    qdev_init_nofail(ds);
+    sysbus_mmio_map(SYS_BUS_DEVICE(ds), 0, 0x92300000);
+    sysbus_connect_irq(SYS_BUS_DEVICE(ds), 0, pic[8]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(ds), 1, pic[9]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(ds), 2, pic[10]);
+    sysbus_connect_irq(SYS_BUS_DEVICE(ds), 3, pic[11]);
+
     /* Serial (FTUART010 which is 16550A compatible) */
     if (serial_hds[0]) {
         serial_mm_init(s->as,
diff --git a/hw/arm/ftpwmtmr010.c b/hw/arm/ftpwmtmr010.c
new file mode 100644
index 0000000..bfcbc75
--- /dev/null
+++ b/hw/arm/ftpwmtmr010.c
@@ -0,0 +1,246 @@
+/*
+ * Faraday FTPWMTMR010 Timer.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su <address@hidden>
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#include <hw/hw.h>
+#include <hw/sysbus.h>
+#include <qemu/timer.h>
+#include <sysemu/sysemu.h>
+
+#include "faraday.h"
+#include "ftpwmtmr010.h"
+
+#define TYPE_FTPWMTMR010        "ftpwmtmr010"
+#define TYPE_FTPWMTMR010_TIMER  "ftpwmtmr010_timer"
+
+typedef struct Ftpwmtmr010State Ftpwmtmr010State;
+
+typedef struct Ftpwmtmr010Timer {
+    uint32_t ctrl;
+    uint32_t cntb;
+    int id;
+    uint64_t timeout;
+    uint64_t countdown;
+    qemu_irq irq;
+    QEMUTimer *qtimer;
+    Ftpwmtmr010State *chip;
+} Ftpwmtmr010Timer;
+
+struct Ftpwmtmr010State {
+    SysBusDevice busdev;
+
+    MemoryRegion iomem;
+    Ftpwmtmr010Timer timer[8];
+    uint32_t freq;        /* desired source clock */
+    uint32_t step;        /* get_ticks_per_sec() / freq */
+    uint32_t stat;
+};
+
+#define FTPWMTMR010(obj) \
+    OBJECT_CHECK(Ftpwmtmr010State, obj, TYPE_FTPWMTMR010)
+
+static uint64_t ftpwmtmr010_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+    Ftpwmtmr010State *s = FTPWMTMR010(opaque);
+    Ftpwmtmr010Timer *t;
+    uint64_t now = qemu_get_clock_ns(vm_clock);
+    uint64_t ret = 0;
+
+    if (addr == REG_STAT) {
+        ret = s->stat;
+    } else if (addr >= REG_TIMER_BASE(1) && addr < REG_TIMER_BASE(9)) {
+        t = s->timer + (addr >> 4) - 1;
+        switch (addr & 0x0f) {
+        case REG_TIMER_CTRL:
+            return t->ctrl;
+        case REG_TIMER_CNTB:
+            return t->cntb;
+        case REG_TIMER_CNTO:
+            if ((t->ctrl & TIMER_CTRL_START) && (t->timeout > now)) {
+                ret = (t->timeout - now) / s->step;
+            }
+            break;
+        }
+    }
+
+    return ret;
+}
+
+static void ftpwmtmr010_mem_write(void    *opaque,
+                                  hwaddr   addr,
+                                  uint64_t val,
+                                  unsigned size)
+{
+    Ftpwmtmr010State *s = FTPWMTMR010(opaque);
+    Ftpwmtmr010Timer *t;
+
+    if (addr == REG_STAT) {
+        int i;
+        s->stat &= ~((uint32_t)val & 0xffffffff);
+        for (i = 0; i < 8; ++i) {
+            if (val & (1 << i)) {
+                qemu_irq_lower(s->timer[i].irq);
+            }
+        }
+    } else if (addr >= REG_TIMER_BASE(1) && addr < REG_TIMER_BASE(9)) {
+        t = s->timer + (addr >> 4) - 1;
+        switch (addr & 0x0f) {
+        case REG_TIMER_CTRL:
+            t->ctrl = (uint32_t)val;
+            if (t->ctrl & TIMER_CTRL_UPDATE) {
+                t->countdown = (uint64_t)t->cntb * (uint64_t)s->step;
+            }
+            if (t->ctrl & TIMER_CTRL_START) {
+                t->timeout = t->countdown + qemu_get_clock_ns(vm_clock);
+                qemu_mod_timer(t->qtimer, t->timeout);
+            }
+            break;
+        case REG_TIMER_CNTB:
+            t->cntb = (uint32_t)val;
+            break;
+        }
+    }
+}
+
+static const MemoryRegionOps ftpwmtmr010_ops = {
+    .read  = ftpwmtmr010_mem_read,
+    .write = ftpwmtmr010_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ftpwmtmr010_timer_tick(void *opaque)
+{
+    Ftpwmtmr010Timer *t = opaque;
+    Ftpwmtmr010State *s = t->chip;
+
+    /* if the timer has been enabled/started */
+    if (!(t->ctrl & (1 << 1))) {
+        return;
+    }
+
+    /* if the interrupt enabled */
+    if (t->ctrl & (1 << 5)) {
+        s->stat |= 1 << t->id;
+        if (t->ctrl & (1 << 6)) {
+            qemu_irq_pulse(t->irq);
+        } else {
+            qemu_irq_raise(t->irq);
+        }
+    }
+
+    /* if auto-reload is enabled */
+    if (t->ctrl & (1 << 4)) {
+        t->timeout = t->countdown + qemu_get_clock_ns(vm_clock);
+        qemu_mod_timer(t->qtimer, t->timeout);
+    } else {
+        t->ctrl &= ~(1 << 1);
+    }
+}
+
+static void ftpwmtmr010_reset(DeviceState *ds)
+{
+    SysBusDevice *busdev = SYS_BUS_DEVICE(ds);
+    Ftpwmtmr010State *s = FTPWMTMR010(FROM_SYSBUS(Ftpwmtmr010State, busdev));
+    int i;
+
+    s->stat = 0;
+
+    for (i = 0; i < 8; ++i) {
+        s->timer[i].ctrl = 0;
+        s->timer[i].cntb = 0;
+        s->timer[i].timeout = 0;
+        qemu_irq_lower(s->timer[i].irq);
+        qemu_del_timer(s->timer[i].qtimer);
+    }
+}
+
+static int ftpwmtmr010_init(SysBusDevice *busdev)
+{
+    Ftpwmtmr010State *s = FTPWMTMR010(FROM_SYSBUS(Ftpwmtmr010State, busdev));
+    int i;
+
+    s->step = (uint64_t)get_ticks_per_sec() / (uint64_t)s->freq;
+
+    DPRINTF("ftpwmtmr010 freq=%d\n", s->freq);
+
+    memory_region_init_io(&s->iomem,
+                          &ftpwmtmr010_ops,
+                          s,
+                          TYPE_FTPWMTMR010,
+                          0x1000);
+    sysbus_init_mmio(busdev, &s->iomem);
+    for (i = 0; i < 8; ++i) {
+        s->timer[i].id = i;
+        s->timer[i].chip = s;
+        s->timer[i].qtimer = qemu_new_timer_ns(
+                                vm_clock,
+                                ftpwmtmr010_timer_tick,
+                                &s->timer[i]);
+        sysbus_init_irq(busdev, &s->timer[i].irq);
+    }
+
+    return 0;
+}
+
+static const VMStateDescription vmstate_ftpwmtmr010_timer = {
+    .name = TYPE_FTPWMTMR010_TIMER,
+    .version_id = 2,
+    .minimum_version_id = 2,
+    .minimum_version_id_old = 2,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(ctrl, Ftpwmtmr010Timer),
+        VMSTATE_UINT32(cntb, Ftpwmtmr010Timer),
+        VMSTATE_END_OF_LIST(),
+    },
+};
+
+static const VMStateDescription vmstate_ftpwmtmr010 = {
+    .name = TYPE_FTPWMTMR010,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(stat, Ftpwmtmr010State),
+        VMSTATE_UINT32(freq, Ftpwmtmr010State),
+        VMSTATE_UINT32(step, Ftpwmtmr010State),
+        VMSTATE_STRUCT_ARRAY(timer, Ftpwmtmr010State, 8, 1,
+                        vmstate_ftpwmtmr010_timer, Ftpwmtmr010Timer),
+        VMSTATE_END_OF_LIST(),
+    }
+};
+
+static Property ftpwmtmr010_properties[] = {
+    DEFINE_PROP_UINT32("freq", Ftpwmtmr010State, freq, 66000000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ftpwmtmr010_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    k->init     = ftpwmtmr010_init;
+    dc->vmsd    = &vmstate_ftpwmtmr010;
+    dc->props   = ftpwmtmr010_properties;
+    dc->reset   = ftpwmtmr010_reset;
+    dc->no_user = 1;
+}
+
+static const TypeInfo ftpwmtmr010_info = {
+    .name          = TYPE_FTPWMTMR010,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Ftpwmtmr010State),
+    .class_init    = ftpwmtmr010_class_init,
+};
+
+static void ftpwmtmr010_register_types(void)
+{
+    type_register_static(&ftpwmtmr010_info);
+}
+
+type_init(ftpwmtmr010_register_types)
diff --git a/hw/arm/ftpwmtmr010.h b/hw/arm/ftpwmtmr010.h
new file mode 100644
index 0000000..83f572a
--- /dev/null
+++ b/hw/arm/ftpwmtmr010.h
@@ -0,0 +1,25 @@
+/*
+ * Faraday FTPWMTMR010 Timer.
+ *
+ * Copyright (c) 2012 Faraday Technology
+ * Written by Dante Su <address@hidden>
+ *
+ * This code is licensed under GNU GPL v2+.
+ */
+
+#ifndef HW_ARM_FTPWMTMR010_H
+#define HW_ARM_FTPWMTMR010_H
+
+#define REG_STAT            0x00
+#define REG_TIMER_BASE(id)  (0x00 + ((id) << 4))
+#define REG_TIMER_CTRL      0x00
+#define REG_TIMER_CNTB      0x04
+#define REG_TIMER_CMPB      0x08
+#define REG_TIMER_CNTO      0x0C
+
+#define TIMER_CTRL_START        (1 << 1)
+#define TIMER_CTRL_UPDATE       (1 << 2)
+#define TIMER_CTRL_AUTORELOAD   (1 << 4)
+#define TIMER_CTRL_INTEN        (1 << 5)
+
+#endif
-- 
1.7.9.5