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[Qemu-devel] [RFC qom-cpu v2 05/28] target-openrisc: Update OpenRISCCPU
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [RFC qom-cpu v2 05/28] target-openrisc: Update OpenRISCCPU to QOM realizefn |
Date: |
Sun, 20 Jan 2013 08:22:28 +0100 |
Update the openrisc_cpu_realize() signature, hook it up to
DeviceClass::realize and set realized = true in cpu_openrisc_init().
qapi/error.h is now included through qdev and no longer needed.
Signed-off-by: Andreas Färber <address@hidden>
---
target-openrisc/cpu.c | 13 ++++++++++---
target-openrisc/cpu.h | 4 ++--
2 Dateien geändert, 12 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 7a55112..d0b2fc6 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -62,12 +62,15 @@ static inline void set_feature(OpenRISCCPU *cpu, int
feature)
cpu->env.cpucfgr = cpu->feature;
}
-void openrisc_cpu_realize(Object *obj, Error **errp)
+static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
{
- OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+ OpenRISCCPU *cpu = OPENRISC_CPU(dev);
+ OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu));
+
+ occ->parent_realize(dev, errp);
}
static void openrisc_cpu_initfn(Object *obj)
@@ -117,6 +120,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void
*data)
{
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(occ);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ occ->parent_realize = dc->realize;
+ dc->realize = openrisc_cpu_realizefn;
occ->parent_reset = cc->reset;
cc->reset = openrisc_cpu_reset;
@@ -165,7 +172,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
cpu = OPENRISC_CPU(object_new(cpu_model));
cpu->env.cpu_model_str = cpu_model;
- openrisc_cpu_realize(OBJECT(cpu), NULL);
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 3beab45..419f007 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -33,7 +33,6 @@ struct OpenRISCCPU;
#include "exec/cpu-defs.h"
#include "fpu/softfloat.h"
#include "qom/cpu.h"
-#include "qapi/error.h"
#define TYPE_OPENRISC_CPU "or32-cpu"
@@ -46,6 +45,7 @@ struct OpenRISCCPU;
/**
* OpenRISCCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A OpenRISC CPU model.
@@ -55,6 +55,7 @@ typedef struct OpenRISCCPUClass {
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} OpenRISCCPUClass;
@@ -340,7 +341,6 @@ static inline OpenRISCCPU
*openrisc_env_get_cpu(CPUOpenRISCState *env)
#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
-void openrisc_cpu_realize(Object *obj, Error **errp);
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s);
--
1.7.10.4
- [Qemu-devel] [RFC qom-cpu v2 06/28] target-ppc: Update PowerPCCPU to QOM realizefn, (continued)
- [Qemu-devel] [RFC qom-cpu v2 06/28] target-ppc: Update PowerPCCPU to QOM realizefn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 09/28] target-m68k: Introduce QOM realizefn for M68kCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 11/28] target-mips: Introduce QOM realizefn for MIPSCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 13/28] target-sh4: Introduce QOM realizefn for SuperHCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 12/28] target-s390x: Introduce QOM realizefn for S390CPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 10/28] target-microblaze: Introduce QOM realizefn for MicroBlazeCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 15/28] target-unicore32: Introduce QOM realizefn for UniCore32CPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 18/28] target-cris: Move TCG initialization to CRISCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 16/28] target-xtensa: Introduce QOM realizefn for XtensaCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 05/28] target-openrisc: Update OpenRISCCPU to QOM realizefn,
Andreas Färber <=
- [Qemu-devel] [RFC qom-cpu v2 14/28] target-sparc: Introduce QOM realizefn for SPARCCPU, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 17/28] target-arm: Move TCG initialization to ARMCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 23/28] target-ppc: Move TCG initialization to PowerPCCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 20/28] target-m68k: Move TCG initialization to M68kCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 19/28] target-lm32: Move TCG initialization to LM32CPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 21/28] target-microblaze: Move TCG initialization to MicroBlazeCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 22/28] target-mips: Move TCG initialization to MIPSCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 26/28] target-sparc: Move TCG initialization to SPARCCPU initfn, Andreas Färber, 2013/01/20
- [Qemu-devel] [RFC qom-cpu v2 27/28] target-unicore32: Move TCG initialization to UniCore32CPU initfn, Andreas Färber, 2013/01/20