[Qemu-devel] [PATCH] target-arm: add Faraday ARMv5TE processors support

[Dante]

Faraday processors are a series of ARMv4/ARMv5TE clone.

* ARMv4 series (FA526, FA626).
    All of them are now out-of-date, so I have no plan for them.

* ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE)
    All the single core RISC listed above are included in this patch.
    And there are two Faraday CP15 extensions (AUX and I/D-Scratchpad)
    have been implemented as NOP.
    
Signed-off-by: Kuo-Jung Su <address@hidden>
---
 target-arm/cpu.c    |   52 +++++++++++++++++++++++++++++++++++++++++++++++++++
 target-arm/cpu.h    |    1 +
 target-arm/helper.c |   15 +++++++++++++++
 3 files changed, 68 insertions(+)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 07588a1..363826b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -214,6 +214,54 @@ static void arm926_initfn(Object *obj)
     cpu->reset_sctlr = 0x00090078;
 }
 
+static void fa606te_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    set_feature(&cpu->env, ARM_FEATURE_V5);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_MPU);
+    set_feature(&cpu->env, ARM_FEATURE_FARADAY);
+    cpu->midr = 0x66056061;                    /* CR0-0 Identification Code 
Register (ID) */
+    cpu->ctr = 0x00000000;                     /* CR0-1 Cache Type Register 
(CTR) */
+    cpu->reset_sctlr = 0x00000078;     /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa616te_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    set_feature(&cpu->env, ARM_FEATURE_V5);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+    set_feature(&cpu->env, ARM_FEATURE_FARADAY);
+    cpu->midr = 0x66056161;                    /* CR0-0 Identification Code 
Register (ID) */
+    cpu->ctr = 0x1d152152;                     /* CR0-1 Cache Type Register 
(CTR) */
+    cpu->reset_sctlr = 0x00050078;     /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa626te_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    set_feature(&cpu->env, ARM_FEATURE_V5);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+    set_feature(&cpu->env, ARM_FEATURE_FARADAY);
+    cpu->midr = 0x66056261;                    /* CR0-0 Identification Code 
Register (ID) */
+    cpu->ctr = 0x0f192192;                     /* CR0-1 Cache Type Register 
(CTR) */
+    cpu->reset_sctlr = 0x00000078;     /* CR1-0 Configuration Register (CFG) */
+}
+
+static void fa726te_initfn(Object *obj)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+    set_feature(&cpu->env, ARM_FEATURE_V5);
+    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
+    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
+    set_feature(&cpu->env, ARM_FEATURE_FARADAY);
+    cpu->midr = 0x66057261;                    /* CR0-0 Identification Code 
Register (ID) */
+    cpu->ctr = 0x1d192192;                     /* CR0-1 Cache Type Register 
(CTR) */
+    cpu->reset_sctlr = 0x00050078;     /* CR1-0 Configuration Register (CFG) */
+}
+
 static void arm946_initfn(Object *obj)
 {
     ARMCPU *cpu = ARM_CPU(obj);
@@ -726,6 +774,10 @@ typedef struct ARMCPUInfo {
 
 static const ARMCPUInfo arm_cpus[] = {
     { .name = "arm926",      .initfn = arm926_initfn },
+    { .name = "fa606te",     .initfn = fa606te_initfn },
+    { .name = "fa616te",     .initfn = fa616te_initfn },
+    { .name = "fa626te",     .initfn = fa626te_initfn },
+    { .name = "fa726te",     .initfn = fa726te_initfn },
     { .name = "arm946",      .initfn = arm946_initfn },
     { .name = "arm1026",     .initfn = arm1026_initfn },
     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ffddfcb..e206b99 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -391,6 +391,7 @@ enum arm_features {
     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
+    ARM_FEATURE_FARADAY, /* Faraday extensions */
 };
 
 static inline int arm_feature(CPUARMState *env, int feature)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 37c34a1..d398c6c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1015,6 +1015,18 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
     REGINFO_SENTINEL
 };
 
+static const ARMCPRegInfo faraday_cp_reginfo[] = {
+    /* Auxiliary Control Register */
+    { .name = "AUXCTR", .cp = 15, .crn = 1, .crm = 0,
+      .opc1 = 0, .opc2 = 1, .access = PL1_RW,
+      .type = ARM_CP_NOP },
+    /* I/D-Scratchpad Configuration Register */
+    { .name = "IDSCFG", .cp = 15, .crn = 9, .crm = 1,
+      .opc1 = 0, .opc2 = CP_ANY, .access = PL1_RW,
+      .type = ARM_CP_NOP },
+    REGINFO_SENTINEL
+};
+
 static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t 
value)
 {
     env->cp15.c1_sys = value;
@@ -1163,6 +1175,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_LPAE)) {
         define_arm_cp_regs(cpu, lpae_cp_reginfo);
     }
+    if (arm_feature(env, ARM_FEATURE_FARADAY)) {
+        define_arm_cp_regs(cpu, faraday_cp_reginfo);
+    }
     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
      * be read-only (ie write causes UNDEF exception).
-- 
1.7.9.5


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