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[Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup |
Date: |
Wed, 9 Jan 2013 16:27:37 +0100 |
This patch series contains some fixes and cleanup following the merge
of the DSP ASE patches.
Changes v1 -> v2:
- patch 1: unchanged
- patch 2: new patch as suggested by Richard Henderson
- patch 3: updated to use insn_flags from DisasContext
- patch 4: unchanged
- patch 5: fix the cast on the return value
- patch 6: fix the cast on the return value
- patch 7: unchanged
- patch 8: unchanged
Aurelien Jarno (8):
target-mips: fix DSP loads with rd = 0
target-mips: copy insn_flags in DisasContext
target-mips: generate a reserved instruction exception on CPU without DSP
target-mips: add unions to access DSP elements
target-mips: use DSP unions for binary DSP operators
target-mips: use DSP unions for unary DSP operators
target-mips: use DSP unions for reduction add instructions
target-mips: implement DSP (d)append sub-class with TCG
target-mips/dsp_helper.c | 623 ++++++++++---------------------
target-mips/helper.h | 13 -
target-mips/translate.c | 912 ++++++++++++++++++++++++----------------------
3 files changed, 670 insertions(+), 878 deletions(-)
--
1.7.10.4
- [Qemu-devel] [PATCH v2 0/8] target-mips: DSP ASE fixes and cleanup,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 3/8] target-mips: generate a reserved instruction exception on CPU without DSP, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 1/8] target-mips: fix DSP loads with rd = 0, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 4/8] target-mips: add unions to access DSP elements, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 7/8] target-mips: use DSP unions for reduction add instructions, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 8/8] target-mips: implement DSP (d)append sub-class with TCG, Aurelien Jarno, 2013/01/09
- [Qemu-devel] [PATCH v2 5/8] target-mips: use DSP unions for binary DSP operators, Aurelien Jarno, 2013/01/09