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Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO a


From: Jovanovic, Petar
Subject: Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO and SHILOV
Date: Wed, 5 Dec 2012 23:31:10 +0000

hey Eric,

the patch does not have to be rebased since no changes have been made to
these files since I created the patch.

You can try it on clean master with:

wget -O shilo.diff http://patchwork.ozlabs.org/patch/203744/mbox
git am ./shilo.diff

You probably have the previous (not yet committed) INSV patch on your branch
that creates an issue for you when you run 'git am'.

Petar
________________________________________
From: Johnson, Eric
Sent: Wednesday, December 05, 2012 10:36 PM
To: Jovanovic, Petar; address@hidden
Cc: address@hidden; address@hidden; address@hidden; address@hidden
Subject: RE: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO 
and SHILOV

Oops, I forgot.  The contents are OK but 'git am' didn't like the patch.  patch 
had to use fuzz.  This may need to be rebased to latest master.

-Eric

> -----Original Message-----
> From: address@hidden [mailto:qemu-devel-
> address@hidden On Behalf Of Johnson, Eric
> Sent: Wednesday, December 05, 2012 12:42 PM
> To: Jovanovic, Petar; address@hidden
> Cc: address@hidden; address@hidden; address@hidden;
> address@hidden
> Subject: Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> SHILO and SHILOV
>
> > -----Original Message-----
> > From: address@hidden [mailto:qemu-devel-
> > address@hidden On Behalf Of Petar Jovanovic
> > Sent: Tuesday, December 04, 2012 3:29 PM
> > To: address@hidden
> > Cc: address@hidden; Jovanovic, Petar; address@hidden;
> > address@hidden; address@hidden
> > Subject: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> > SHILO and SHILOV
> >
> > From: Petar Jovanovic <address@hidden>
> >
> > helper_shilo has not been shifting an accumulator value correctly for
> > negative
> > values in 'shift' field. Minor optimization for shift=0 case.
> > This change also adds tests that will trigger issue and check for
> > regressions.
> >
> > Signed-off-by: Petar Jovanovic <address@hidden>
> > ---
> >  target-mips/dsp_helper.c           |   17 +++++++++--------
> >  tests/tcg/mips/mips32-dsp/shilo.c  |   18 ++++++++++++++++++
> >  tests/tcg/mips/mips32-dsp/shilov.c |   20 ++++++++++++++++++++
> >  3 files changed, 47 insertions(+), 8 deletions(-)
> >
> > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> > index e7949c2..44f6dc7 100644
> > --- a/target-mips/dsp_helper.c
> > +++ b/target-mips/dsp_helper.c
> > @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong
> > rs, CPUMIPSState *env)
> >
> >      rs5_0 = rs & 0x3F;
> >      rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
> > -    rs5_0 = MIPSDSP_ABS(rs5_0);
> > +
> > +    if (unlikely(rs5_0 == 0)) {
> > +        return;
> > +    }
> > +
> >      acc   = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
> >              ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
> > -    if (rs5_0 == 0) {
> > -        temp = acc;
> > +
> > +    if (rs5_0 > 0) {
> > +        temp = acc >> rs5_0;
> >      } else {
> > -        if (rs5_0 > 0) {
> > -            temp = acc >> rs5_0;
> > -        } else {
> > -            temp = acc << rs5_0;
> > -        }
> > +        temp = acc << -rs5_0;
> >      }
> >
> >      env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp &
> MIPSDSP_LHI)
> > >> 32);
> > diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-
> > dsp/shilo.c
> > index b686616..ce8ebc6 100644
> > --- a/tests/tcg/mips/mips32-dsp/shilo.c
> > +++ b/tests/tcg/mips/mips32-dsp/shilo.c
> > @@ -23,5 +23,23 @@ int main()
> >      assert(ach == resulth);
> >      assert(acl == resultl);
> >
> > +
> > +    ach = 0x1;
> > +    acl = 0x80000000;
> > +
> > +    resulth = 0x3;
> > +    resultl = 0x0;
> > +
> > +    __asm
> > +        ("mthi %0, $ac1\n\t"
> > +         "mtlo %1, $ac1\n\t"
> > +         "shilo $ac1, -1\n\t"
> > +         "mfhi %0, $ac1\n\t"
> > +         "mflo %1, $ac1\n\t"
> > +         : "+r"(ach), "+r"(acl)
> > +        );
> > +    assert(ach == resulth);
> > +    assert(acl == resultl);
> > +
> >      return 0;
> >  }
> > diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-
> > dsp/shilov.c
> > index f186032..e1d6cea 100644
> > --- a/tests/tcg/mips/mips32-dsp/shilov.c
> > +++ b/tests/tcg/mips/mips32-dsp/shilov.c
> > @@ -25,5 +25,25 @@ int main()
> >      assert(ach == resulth);
> >      assert(acl == resultl);
> >
> > +
> > +    rs  = 0xffffffff;
> > +    ach = 0x1;
> > +    acl = 0x80000000;
> > +
> > +    resulth = 0x3;
> > +    resultl = 0x0;
> > +
> > +    __asm
> > +        ("mthi %0, $ac1\n\t"
> > +         "mtlo %1, $ac1\n\t"
> > +         "shilov $ac1, %2\n\t"
> > +         "mfhi %0, $ac1\n\t"
> > +         "mflo %1, $ac1\n\t"
> > +         : "+r"(ach), "+r"(acl)
> > +         : "r"(rs)
> > +        );
> > +    assert(ach == resulth);
> > +    assert(acl == resultl);
> > +
> >      return 0;
> >  }
> > --
> > 1.7.5.4
> >
>
> Reviewed-by: Eric Johnson <address@hidden>




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