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Re: [Qemu-devel] [PATCH 6/7] tcg: Streamline movcond_i64 using 32-bit ar
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 6/7] tcg: Streamline movcond_i64 using 32-bit arithmetic |
Date: |
Sat, 22 Sep 2012 20:11:12 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Fri, Sep 21, 2012 at 10:13:39AM -0700, Richard Henderson wrote:
> Avoiding 64-bit arithmetic (outside of the compare) reduces the
> generated op count from 15 to 12, and the generated code size on
> i686 from 105 to 88 bytes.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> tcg/tcg-op.h | 42 +++++++++++++++++++++++++++++++-----------
> 1 file changed, 31 insertions(+), 11 deletions(-)
>
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 6d28f82..3e375ea 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2141,18 +2141,38 @@ static inline void tcg_gen_movcond_i64(TCGCond cond,
> TCGv_i64 ret,
> TCGv_i64 c1, TCGv_i64 c2,
> TCGv_i64 v1, TCGv_i64 v2)
> {
> - if (TCG_TARGET_HAS_movcond_i64) {
> - tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond);
> + if (TCG_TARGET_REG_BITS == 32) {
Using such a construction doesn't compile on a 64-bit host.
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0,
> + TCGV_LOW(c1), TCGV_HIGH(c1),
> + TCGV_LOW(c2), TCGV_HIGH(c2), cond);
Because there TCGV_LOW and TCGV_HIGH do not exist. You should use #ifdef
instead.
> + tcg_gen_neg_i32(t0, t0);
> +
> + tcg_gen_and_i32(t1, TCGV_LOW(v1), t0);
> + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0);
> + tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1);
> +
> + tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0);
> + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0);
> + tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1);
> +
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(t1);
> } else {
> - TCGv_i64 t0 = tcg_temp_new_i64();
> - TCGv_i64 t1 = tcg_temp_new_i64();
> - tcg_gen_setcond_i64(cond, t0, c1, c2);
> - tcg_gen_neg_i64(t0, t0);
> - tcg_gen_and_i64(t1, v1, t0);
> - tcg_gen_andc_i64(ret, v2, t0);
> - tcg_gen_or_i64(ret, ret, t1);
> - tcg_temp_free_i64(t0);
> - tcg_temp_free_i64(t1);
> + if (TCG_TARGET_HAS_movcond_i64) {
> + tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2,
> cond);
> + } else {
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + TCGv_i64 t1 = tcg_temp_new_i64();
> + tcg_gen_setcond_i64(cond, t0, c1, c2);
> + tcg_gen_neg_i64(t0, t0);
> + tcg_gen_and_i64(t1, v1, t0);
> + tcg_gen_andc_i64(ret, v2, t0);
> + tcg_gen_or_i64(ret, ret, t1);
> + tcg_temp_free_i64(t0);
> + tcg_temp_free_i64(t1);
> + }
> }
> }
>
> --
> 1.7.11.4
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH 3/7] tcg-i386: Implement movcond, (continued)
- [Qemu-devel] [PATCH 2/7] target-alpha: Use movcond, Richard Henderson, 2012/09/21
- [Qemu-devel] [PATCH 5/7] tcg: Optimize two-address commutative operations, Richard Henderson, 2012/09/21
- [Qemu-devel] [PATCH 6/7] tcg: Streamline movcond_i64 using 32-bit arithmetic, Richard Henderson, 2012/09/21
- Re: [Qemu-devel] [PATCH v2 0/7] tcg: movcond, Aurelien Jarno, 2012/09/21
- Re: [Qemu-devel] [PATCH v2 0/7] tcg: movcond (ppc32 version), malc, 2012/09/21