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Re: [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversio
From: |
Max Filippov |
Subject: |
Re: [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversions |
Date: |
Sun, 9 Sep 2012 22:39:30 +0400 |
On Sun, Sep 9, 2012 at 9:24 PM, Marc Gauthier <address@hidden> wrote:
> Hi Max,
>
> Max Filippov wrote:
>> On Sun, Sep 9, 2012 at 8:16 PM, Peter Maydell
>> <address@hidden> wrote:
>> > On 9 September 2012 17:04, Max Filippov <address@hidden> wrote:
>> >> These are FP to integer and integer to FP conversion opcodes.
>> >> See ISA, 4.3.10 for more details.
>> >>
>> >> Note that utrunc.s implementation follows ISS behaviour, not ISA.
>> >
>> > ISS here means "instruction set simulator", right? Do you
>> > have any actual silicon you can check behaviour against?
>> > Basically there are three votes here (documentation, simulator
>> > and silicon) and QEMU should follow the majority opinion in
>> > the absence of any more official word.
>>
>> I have no silicon core with FP and I doubt that I can easily
>> access one.
>> IIUC Tensilica ISS core-specific code is autogenerated from
>> the hardware
>> description, without human intervention.
>> Looks like it's either documentation error or silicon error, probably
>> there's an erratum issued. Marc, can you please comment?
>
> If it's the Tensilica ISS, behavior indeed should match hardware,
> from a common description (am simplifying, but I expect here this
> to hold). It also depends on which release of hardware/ISS
> (do you know that exactly?).
ISS is from the RC-2010.2-linux package, xt-run --help shows the following:
Xtensa 8.0.2 Instruction Set Simulator
core-isa.h for the core on which I run tests has the following:
#define XCHAL_SW_VERSION 800002 /* sw version of this header */
#define XCHAL_CORE_ID "dsp3400_RC2" /* alphanum core name
(CoreID) set in the Xtensa
Processor Generator */
#define XCHAL_BUILD_UNIQUE_ID 0x0002DC22 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
#define XCHAL_HW_CONFIGID0 0xC3F3DBFE /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1082C3B0 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX3.0.1" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2300 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 230001 /* major*100+minor */
--
Thanks.
-- Max
- Re: [Qemu-devel] [PATCH v2 02/10] softfloat: add NO_SIGNALING_NANS, (continued)
- [Qemu-devel] [PATCH v2 03/10] target-xtensa: handle boolean option in overlays, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 04/10] target-xtensa: specialize softfloat NaN rules, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 05/10] target-xtensa: add FP registers, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 06/10] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 07/10] target-xtensa: implement FP0 arithmetic, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversions, Max Filippov, 2012/09/09
[Qemu-devel] [PATCH v2 09/10] target-xtensa: implement FP1 group, Max Filippov, 2012/09/09
[Qemu-devel] [PATCH v2 10/10] target-xtensa: implement coprocessor context option, Max Filippov, 2012/09/09