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[Qemu-devel] [PATCH 24/24] openpic: Added BRR1 register
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 24/24] openpic: Added BRR1 register |
Date: |
Wed, 15 Aug 2012 11:59:02 +0200 |
From: Bharat Bhushan <address@hidden>
Linux mpic driver uses (changes may be in pipeline to get upstreamed soon)
BRR1. This patch adds the support to emulate readonly FSL BRR1 register.
Currently QEMU does not fully emulate any version on MPIC, so the MPIC
Major number and Minor number are set to 0.
Signed-off-by: Bharat Bhushan <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/openpic.c | 17 +++++++++++++++++
1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 58ef871..b9d8568 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -130,6 +130,17 @@ enum {
#define MPIC_CPU_REG_START 0x20000
#define MPIC_CPU_REG_SIZE 0x100 + ((MAX_CPU - 1) * 0x1000)
+/*
+ * Block Revision Register1 (BRR1): QEMU does not fully emulate
+ * any version on MPIC. So to start with, set the IP version to 0.
+ *
+ * NOTE: This is Freescale MPIC specific register. Keep it here till
+ * this code is refactored for different variants of OPENPIC and MPIC.
+ */
+#define FSL_BRR1_IPID (0x0040 << 16) /* 16 bit IP-block ID */
+#define FSL_BRR1_IPMJ (0x00 << 8) /* 8 bit IP major number */
+#define FSL_BRR1_IPMN 0x00 /* 8 bit IP minor number */
+
enum mpic_ide_bits {
IDR_EP = 31,
IDR_CI0 = 30,
@@ -595,6 +606,8 @@ static void openpic_gbl_write (void *opaque,
target_phys_addr_t addr, uint32_t v
if (addr & 0xF)
return;
switch (addr) {
+ case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
+ break;
case 0x40:
case 0x50:
case 0x60:
@@ -671,6 +684,7 @@ static uint32_t openpic_gbl_read (void *opaque,
target_phys_addr_t addr)
case 0x1090: /* PINT */
retval = 0x00000000;
break;
+ case 0x00: /* Block Revision Register1 (BRR1) */
case 0x40:
case 0x50:
case 0x60:
@@ -893,6 +907,9 @@ static uint32_t openpic_cpu_read_internal(void *opaque,
target_phys_addr_t addr,
dst = &opp->dst[idx];
addr &= 0xFF0;
switch (addr) {
+ case 0x00: /* Block Revision Register1 (BRR1) */
+ retval = FSL_BRR1_IPID | FSL_BRR1_IPMJ | FSL_BRR1_IPMN;
+ break;
case 0x80: /* PCTP */
retval = dst->pctp;
break;
--
1.6.0.2
- [Qemu-devel] [PATCH 13/24] PPC: spapr: Remove global variable, (continued)
- [Qemu-devel] [PATCH 13/24] PPC: spapr: Remove global variable, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 10/24] spapr: Add support for -vga option, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 12/24] PPC: spapr: Rework VGA select logic, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 15/24] pseries: Remove extraneous prints, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 19/24] pseries: Export find_phb() utility function for PCI code, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 17/24] pseries: Separate PCI RTAS setup from common from emulation specific PCI setup, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 16/24] pseries: Rework irq assignment to avoid carrying qemu_irqs around, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 22/24] pseries dma: DMA window params added to PHB and DT population changed, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 20/24] pseries: Add trace event for PCI irqs, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 23/24] pseries: Update SLOF firmware image, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 24/24] openpic: Added BRR1 register,
Alexander Graf <=
- [Qemu-devel] [PATCH 21/24] pseries: Add PCI MSI/MSI-X support, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 18/24] pseries: added allocator for a block of IRQs, Alexander Graf, 2012/08/15
- [Qemu-devel] [PATCH 14/24] pseries: Update SLOF, Alexander Graf, 2012/08/15
- Re: [Qemu-devel] [PULL 00/24] ppc patch queue 2012-08-15, Anthony Liguori, 2012/08/15