Re: [Qemu-devel] Keeping a secondary CPU in reset

[Andreas Färber]

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Hi Thierry,

Am 17.07.2012 17:46, schrieb Thierry Reding:
> I've been toying around with adding NVIDIA Tegra support to QEMU.
> While adding SMP support I came across a problem: on Tegra, the
> secondary CPU is kept in reset by the clock-and-reset controller
> (CRC). When bringing up the secondary CPU, the OS writes a given
> register in the CRC to release the CPU, after which it starts
> running. Other hardware blocks can also be reset by writing other
> registers in the CRC.
[snip]

Please take a look at the Tegra feature page on the Wiki, which has a
link to my repository where I've been rebasing an older series by
Vincent Palatin.

http://wiki.qemu.org/Features/Tegra2

It does not use the generic arm_boot iirc but its own implementation.
There's a tegra_clocks device that probably corresponds to the CRC.

What's still missing on my branch is the actual machine that
instantiates the devices I've been working on.
A big TODO where I could use some help is refactoring EHCI so that we
can have the current PCIDevice plus a new SysBus device (or
DeviceState?) for Tegra.

Regards,
Andreas

- -- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


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