Re: [Qemu-devel] [PATCH v6 11/16] target-or32: Add a IIS dummy board

[Peter Crosthwaite]

On Mon, Jun 25, 2012 at 12:23 PM, Jia Liu <address@hidden> wrote:
> Hi Peter,
>
> On Thu, Jun 21, 2012 at 5:03 PM, Peter Crosthwaite
> <address@hidden> wrote:
>> On Thu, Jun 21, 2012 at 12:58 PM, Jia Liu <address@hidden> wrote:
>>> Add a IIS dummy board.
>>>
>>> Signed-off-by: Jia Liu <address@hidden>
>>> ---
>>>  hw/openrisc/Makefile.objs |    2 +-
>>>  hw/openrisc_sim.c         |  160 
>>> +++++++++++++++++++++++++++++++++++++++++++++
>>>  2 files changed, 161 insertions(+), 1 deletion(-)
>>>  create mode 100644 hw/openrisc_sim.c
>>>
>>> diff --git a/hw/openrisc/Makefile.objs b/hw/openrisc/Makefile.objs
>>> index 1c541a5..38ff8f5 100644
>>> --- a/hw/openrisc/Makefile.objs
>>> +++ b/hw/openrisc/Makefile.objs
>>> @@ -1,3 +1,3 @@
>>> -obj-y = openrisc_pic.o openrisc_timer.o
>>> +obj-y = openrisc_pic.o openrisc_sim.o openrisc_timer.o
>>>
>>>  obj-y := $(addprefix ../,$(obj-y))
>>> diff --git a/hw/openrisc_sim.c b/hw/openrisc_sim.c
>>> new file mode 100644
>>> index 0000000..892c67f
>>> --- /dev/null
>>> +++ b/hw/openrisc_sim.c
>>> @@ -0,0 +1,160 @@
>>> +/*
>>> + *  OpenRISC simulator for use as an ISS.
>>> + *
>>> + *  Copyright (c) 2011-2012 Jia Liu <address@hidden>
>>> + *                          Feng Gao <address@hidden>
>>> + *
>>> + * This library is free software; you can redistribute it and/or
>>> + * modify it under the terms of the GNU Lesser General Public
>>> + * License as published by the Free Software Foundation; either
>>> + * version 2 of the License, or (at your option) any later version.
>>> + *
>>> + * This library is distributed in the hope that it will be useful,
>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
>>> + * Lesser General Public License for more details.
>>> + *
>>> + * You should have received a copy of the GNU Lesser General Public
>>> + * License along with this library; if not, see 
>>> <http://www.gnu.org/licenses/>.
>>> + */
>>> +
>>> +#include "hw.h"
>>> +#include "openrisc_cpudev.h"
>>> +#include "boards.h"
>>> +#include "elf.h"
>>> +#include "pc.h"
>>> +#include "loader.h"
>>> +#include "exec-memory.h"
>>> +#include "sysemu.h"
>>> +#include "sysbus.h"
>>> +#include "qtest.h"
>>> +
>>> +#define KERNEL_LOAD_ADDR 0x100
>>> +
>>> +static struct _loaderparams {
>>> +    uint64_t ram_size;
>>> +    const char *kernel_filename;
>>> +    const char *kernel_cmdline;
>>> +    const char *initrd_filename;
>>> +} loaderparams;
>>> +
>>> +static void main_cpu_reset(void *opaque)
>>> +{
>>> +    CPUOpenRISCState *env = opaque;
>>> +    cpu_reset(ENV_GET_CPU(env));
>>> +}
>>> +
>>> +static void openrisc_sim_net_init(MemoryRegion *address_space,
>>> +                                  target_phys_addr_t base,
>>> +                                  target_phys_addr_t descriptors,
>>> +                                  qemu_irq irq, NICInfo *nd)
>>> +{
>>> +    DeviceState *dev;
>>> +    SysBusDevice *s;
>>> +
>>> +    dev = qdev_create(NULL, "open_eth");
>>> +    qdev_set_nic_properties(dev, nd);
>>> +    qdev_init_nofail(dev);
>>> +
>>> +    s = sysbus_from_qdev(dev);
>>> +    sysbus_connect_irq(s, 0, irq);
>>> +    memory_region_add_subregion(address_space, base,
>>> +                                sysbus_mmio_get_region(s, 0));
>>> +    memory_region_add_subregion(address_space, descriptors,
>>> +                                sysbus_mmio_get_region(s, 1));
>>> +}
>>> +
>>> +static uint64_t openrisc_load_kernel(void)
>>> +{
>>> +    long kernel_size;
>>> +    uint64_t elf_entry;
>>> +    target_phys_addr_t entry;
>>> +
>>> +    if (loaderparams.kernel_filename && !qtest_enabled()) {
>>> +        kernel_size = load_elf(loaderparams.kernel_filename, NULL, NULL,
>>> +                               &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
>>> +        entry = elf_entry;
>>> +        if (kernel_size < 0) {
>>> +            kernel_size = load_uimage(loaderparams.kernel_filename,
>>> +                                      &entry, NULL, NULL);
>>> +        }
>>> +        if (kernel_size < 0) {
>>> +            kernel_size = load_image_targphys(loaderparams.kernel_filename,
>>> +                                              KERNEL_LOAD_ADDR,
>>> +                                              ram_size - KERNEL_LOAD_ADDR);
>>> +            entry = KERNEL_LOAD_ADDR;
>>> +        }
>>> +        if (kernel_size < 0) {
>>> +            fprintf(stderr, "qemu: could not load kernel '%s'\n",
>>> +                    loaderparams.kernel_filename);
>>> +            exit(1);
>>> +        }
>>> +
>>> +        if (kernel_size > 0) {
>>> +            return elf_entry;
>>> +        }
>>
>> Hi Jia,
>>
>> This seems a little weird. What happens here when it successfully
>> loads a uimage or raw image? It returns the elf_entry (probably == 0)
>> as the load address?
>>
>
> Thank you for pointing this.
> I copy this file from dummy_m68k.c without fully understood, my fault.
>
> Is this code OK?
>

Yep, Looks better.

Regards,
Peter

> static uint64_t openrisc_load_kernel(void)
> {
>    long kernel_size;
>    uint64_t elf_entry;
>    target_phys_addr_t entry;
>
>    if (loaderparams.kernel_filename && !qtest_enabled()) {
>        kernel_size = load_uimage(loaderparams.kernel_filename,
>                                  &entry, NULL, NULL);
>        if (kernel_size < 0) {
>            kernel_size = load_elf(loaderparams.kernel_filename, NULL, NULL,
>                                   &elf_entry, NULL, NULL, 1, ELF_MACHINE, 1);
>            entry = elf_entry;
>        }
>
>        if (kernel_size < 0) {
>            fprintf(stderr, "QEMU: couldn't load the kernel '%s'\n",
>                    loaderparams.kernel_filename);
>            exit(1);
>        }
>    }
>
>    return entry;
> }
>
>
>> Regards,
>> Peter
>>
>>> +    } else {
>>> +        entry = 0;
>>> +    }
>>> +
>>> +    return entry;
>>> +}
>>> +
>>> +static void openrisc_sim_init(ram_addr_t ram_size,
>>> +                              const char *boot_device,
>>> +                              const char *kernel_filename,
>>> +                              const char *kernel_cmdline,
>>> +                              const char *initrd_filename,
>>> +                              const char *cpu_model)
>>> +{
>>> +    CPUOpenRISCState *env;
>>> +    MemoryRegion *ram = g_new(MemoryRegion, 1);
>>> +
>>> +    if (!cpu_model) {
>>> +        cpu_model = "or1200";
>>> +    }
>>> +    env = cpu_init(cpu_model);
>>> +    if (!env) {
>>> +        fprintf(stderr, "Unable to find CPU definition!\n");
>>> +        exit(1);
>>> +    }
>>> +
>>> +    qemu_register_reset(main_cpu_reset, env);
>>> +    main_cpu_reset(env);
>>> +
>>> +    memory_region_init_ram(ram, "openrisc.ram", ram_size);
>>> +    memory_region_add_subregion(get_system_memory(), 0, ram);
>>> +
>>> +    if (kernel_filename) {
>>> +        loaderparams.ram_size = ram_size;
>>> +        loaderparams.kernel_filename = kernel_filename;
>>> +        loaderparams.kernel_cmdline = kernel_cmdline;
>>> +        env->pc = openrisc_load_kernel();
>>> +    }
>>> +
>>> +    cpu_openrisc_pic_init(env);
>>> +    cpu_openrisc_clock_init(env);
>>> +
>>> +    serial_mm_init(get_system_memory(), 0x90000000, 0,
>>> +                   env->irq[2], 115200, serial_hds[0], 
>>> DEVICE_NATIVE_ENDIAN);
>>> +
>>> +    if (nd_table[0].vlan) {
>>> +        openrisc_sim_net_init(get_system_memory(), 0x92000000,
>>> +                              0x92000400, env->irq[4], nd_table);
>>> +    }
>>> +}
>>> +
>>> +static QEMUMachine openrisc_sim_machine = {
>>> +    .name = "or32-sim",
>>> +    .desc = "or32 simulation",
>>> +    .init = openrisc_sim_init,
>>> +    .max_cpus = 1,
>>> +    .is_default = 1,
>>> +};
>>> +
>>> +static void openrisc_sim_machine_init(void)
>>> +{
>>> +    qemu_register_machine(&openrisc_sim_machine);
>>> +}
>>> +
>>> +machine_init(openrisc_sim_machine_init);
>>> --
>>> 1.7.9.5
>>>
>>>
>
> Regards,
> Jia.