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[Qemu-devel] [PATCH 49/72] PPC: e500: dt: create pci node dynamically
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PATCH 49/72] PPC: e500: dt: create pci node dynamically |
Date: |
Sun, 24 Jun 2012 01:07:13 +0200 |
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppce500_mpc8544ds.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
pc-bios/mpc8544ds.dtb | Bin 1810 -> 72 bytes
pc-bios/mpc8544ds.dts | 46 --------------------------------------------
3 files changed, 50 insertions(+), 46 deletions(-)
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
index 03938b2..15df515 100644
--- a/hw/ppce500_mpc8544ds.c
+++ b/hw/ppce500_mpc8544ds.c
@@ -62,6 +62,27 @@ struct boot_info
uint32_t entry;
};
+static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic)
+{
+ int i;
+ const uint32_t tmp[] = {
+ /* IDSEL 0x11 J17 Slot 1 */
+ 0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1,
+ 0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1,
+ 0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1,
+ 0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
+
+ /* IDSEL 0x12 J16 Slot 2 */
+ 0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1,
+ 0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1,
+ 0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1,
+ 0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1,
+ };
+ for (i = 0; i < (7 * 8); i++) {
+ pci_map[i] = cpu_to_be32(tmp[i]);
+ }
+}
+
static int mpc8544_load_device_tree(CPUPPCState *env,
target_phys_addr_t addr,
uint32_t ramsize,
@@ -86,6 +107,11 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
char mpic[128];
uint32_t mpic_ph;
char gutil[128];
+ char pci[128];
+ uint32_t pci_map[7 * 8];
+ uint32_t pci_ranges[12] = { 0x2000000, 0x0, 0xc0000000, 0xc0000000, 0x0,
+ 0x20000000, 0x1000000, 0x0, 0x0, 0xe1000000,
+ 0x0, 0x10000 };
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (!filename) {
@@ -256,6 +282,30 @@ static int mpc8544_load_device_tree(CPUPPCState *env,
MPC8544_CCSRBAR_BASE, 0x1000);
qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
+ snprintf(pci, sizeof(pci), "/address@hidden", MPC8544_PCI_REGS_BASE);
+ qemu_devtree_add_subnode(fdt, pci);
+ qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0);
+ qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
+ qemu_devtree_setprop_string(fdt, pci, "device_type", "pci");
+ qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
+ 0x0, 0x7);
+ pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic));
+ qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map));
+ qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
+ qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2);
+ qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255);
+ for (i = 0; i < 12; i++) {
+ pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
+ }
+ qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
+ qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE,
+ 0x1000);
+ qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666);
+ qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1);
+ qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2);
+ qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3);
+ qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci);
+
ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
if (ret < 0) {
goto out;
diff --git a/pc-bios/mpc8544ds.dtb b/pc-bios/mpc8544ds.dtb
index
25d92f681dec184530af63e2d2cea61cb4cccd04..90ef5c00243b04f4aa3f812b89d5b37c63be09f2
100644
GIT binary patch
literal 72
mcmcb>`|m9S1A_+;TR>?IAT0>Q0zeD{$ZVJxBb31eq&Wct_yhI;
literal 1810
zcmb7EyKdA#6rCkONyI||2}FgEk^-Svaira7i!HW+bSd}&;&>;!qn)*l$3_V>REUy}
ze?a^K5)yPYv~)`kJs<>}GvjgWMJaNn>$&fHJacD0U-|Q0h?VO?h`taPe`CE1z6M?g
zgE}{1|LEk_w^M1INUO+5Lv;y!o5Hq9<address@hidden(9m>$rwvoAt^sw6tLk672uAUvc+l;-6
zob~N2R<>pzWo;R80ZV7GopV_{%aCs{226a^Hy88}`7l}kC9DIZW|@}3VQGKM+AqVt
z$DlbsZg*I36}&&kr!x8;address@hidden>)Ai`wtXS)Bgk&Q
zuQjz<address@hidden|address@hidden;Tj#6Wrt
z_V{>?B(J}P?Elf8gFRiIu#4f$4B|<iZKat^0(address@hidden@8E0B%ZEz0dpFkU
zVWfkyP+ApA8aLy%Fmdtj433Q6nq~G11mm)BQ{*r?oJ8h^h&iNBVAi)i{vY!i+W}%o
z%;OX`dW8Y<ypOvOHgv{*5#k5^o_NNrGY5YY;address@hidden&_?e5CR$gVZC$Z=w
zCSMopE2uSjdzIhv`F>S?%jf%5F)iOhzj_b-U0^QHgZJeYm^HlZ7i7|3Fl`}tj{&6j
z6;address@hidden<@C64LR&*2-aUgzvG!t0xmeSgMt*6AbLnVE~{5ZA$OM&e0oWJ1-(
z;N9&kpZ%8B?=E|g*W7y(3b*bE%t|OWqR}Xq#ssm{+K3IKp2|ud$tNn7kBXB_ia4ER
address@hidden|OD!tPrSVB#%X`(|Fo&sics3US_x$wHRbkE|a2R
zh|{FVQ>|q#HcrDFFs+jEcq^Mk$p{#D-6oL<a#O^4qrxo8f>~syZIi`mVGCEr6r;2(
I0HBzNe~HoS>address@hidden
diff --git a/pc-bios/mpc8544ds.dts b/pc-bios/mpc8544ds.dts
index 4c7bd75..16aba2b 100644
--- a/pc-bios/mpc8544ds.dts
+++ b/pc-bios/mpc8544ds.dts
@@ -11,50 +11,4 @@
/dts-v1/;
/ {
- aliases {
- pci0 = &pci0;
- };
-
- address@hidden {
- mpic: address@hidden {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x40000 0x40000>;
- compatible = "chrp,open-pic";
- device_type = "open-pic";
- };
- };
-
- pci0: address@hidden {
- cell-index = <0>;
- compatible = "fsl,mpc8540-pci";
- device_type = "pci";
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
-
- /* IDSEL 0x11 J17 Slot 1 */
- 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
- 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
- 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
- 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
-
- /* IDSEL 0x12 J16 Slot 2 */
-
- 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
- 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
- 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
- 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
-
- interrupt-parent = <&mpic>;
- interrupts = <24 2>;
- bus-range = <0 255>;
- ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
- 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
- clock-frequency = <66666666>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xe0008000 0x1000>;
- };
};
--
1.6.0.2
- [Qemu-devel] [PATCH 62/72] dt: make setprop argument static, (continued)
- [Qemu-devel] [PATCH 62/72] dt: make setprop argument static, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 72/72] PPC: BookE206: Bump MAS2 to 64bit, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 69/72] PPC: Add e5500 CPU target, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 67/72] PPC: BookE: Implement EPR SPR, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 48/72] PPC: e500: dt: create global-utils node dynamically, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 71/72] PPC: BookE: Support 32 and 64 bit wide MAS2, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 59/72] PPC: e500: Extend address/size of / to 64bit, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 56/72] PPC: e500: Use new MPIC dt format, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 53/72] PPC: e500: dt: use target_phys_addr_t for ramsize, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 54/72] PPC: e500: enable manual loading of dtb blob, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 49/72] PPC: e500: dt: create pci node dynamically,
Alexander Graf <=
- [Qemu-devel] [PATCH 51/72] dt: Add -machine dumpdtb option to dump the current dtb, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 55/72] Revert "dt: temporarily disable subtree creation failure check", Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 70/72] PPC: Extract SPR dump generation into its own function, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 50/72] PPC: e500: dt: start with empty device tree, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 68/72] PPC: BookE: Make ivpr selectable by CPU type, Alexander Graf, 2012/06/23
- [Qemu-devel] [PATCH 57/72] PPC: e500: Use new SOC dt format, Alexander Graf, 2012/06/23
- Re: [Qemu-devel] [PULL 00/72] ppc patch queue 2012-06-24, Blue Swirl, 2012/06/24