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[Qemu-devel] [PATCH 14/33] target-arm: Convert cp15 c3 register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 14/33] target-arm: Convert cp15 c3 register |
Date: |
Wed, 20 Jun 2012 13:27:02 +0100 |
Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 18 ++++++++++++------
1 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2d58eb5..d579a20 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -56,6 +56,13 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf,
int reg)
return 0;
}
+static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
+{
+ env->cp15.c3 = value;
+ tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
+ return 0;
+}
+
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
@@ -63,6 +70,11 @@ static const ARMCPRegInfo cp_reginfo[] = {
*/
{ .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ /* MMU Domain access control / MPU write buffer control */
+ { .name = "DACR", .cp = 15,
+ .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
+ .resetvalue = 0, .writefn = dacr_write },
REGINFO_SENTINEL
};
@@ -1551,10 +1563,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn,
uint32_t val)
}
}
break;
- case 3: /* MMU Domain access control / MPU write buffer control. */
- env->cp15.c3 = val;
- tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
- break;
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */
@@ -1942,8 +1950,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
goto bad_reg;
}
}
- case 3: /* MMU Domain access control / MPU write buffer control. */
- return env->cp15.c3;
case 4: /* Reserved. */
goto bad_reg;
case 5: /* MMU Fault status / MPU access permission. */
--
1.7.1
- [Qemu-devel] [PULL 00/33] target-arm queue, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 10/33] target-arm: Convert WFI/barriers special cases to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 14/33] target-arm: Convert cp15 c3 register,
Peter Maydell <=
- [Qemu-devel] [PATCH 32/33] target-arm: Remove remaining old cp15 infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 09/33] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 31/33] target-arm: Move block cache ops to new cp15 framework, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 08/33] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 30/33] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 02/33] target-arm: initial coprocessor register framework, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 28/33] target-arm: Convert MPIDR, Peter Maydell, 2012/06/20