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[Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PCI co
From: |
Bhushan Bharat-R65777 |
Subject: |
[Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PCI controller (Root Complex) |
Date: |
Fri, 8 Jun 2012 09:03:58 +0000 |
Hi All,
When Freescale PCI controller configured in Root Complex mode then, its
configuration header (type 1) have one inbound BAR (BAR0, called as CCSRBAR).
And rest of BARs (inbound and outbound) are supported by ATMU registers, which
are outside the Type 1 configuration header. This BAR0 of Type 1 configuration
header always translate to CCSR space and is of the size of CCSR. This BAR0
(inbound window) is required for MSI interrupts support. With this window, the
pci devices can write to the MPIC MSI registers to generate MSI interrupt.
As far as I know, as of now no emulated PCI controller supports this BAR0 in
type 1 configuration header. But probably (I think so) that supporting this is
not of big concern, but the point is that this window (BAR0) translate to
mmio-regs (CCSR) and not to DDR memory.
So I have couple of concerns here:
1. Whenever PCI device does need DMA then these windows (inbound and outbound
ATMUs registers) need to used to translate pci address to system physical
address (Sometime we also call this as cpu address space). This will probably
be done by : [Qemu-devel] [PATCH 00/12] IOMMU Infrastructure : patch-set ( I am
trying to understand these patches :-))
2. Hook up this inbound BAR0 in the above patch-set to translate to mmio-regs.
As this would be controller specific, a callback will be registered for
translation. Now it will be upto the controller specific code on how it
translates. As this is needed only for MSI interrupt, maybe, initially we do
not do anything initially, till we want MSI emulation in QEMU.
Please provide your comment.
Thanks
-Bharat
- [Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PCI controller (Root Complex),
Bhushan Bharat-R65777 <=