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[Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registe
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registers to cp_reginfo |
Date: |
Mon, 14 May 2012 20:03:07 +0100 |
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 25 +++++++++++++++++++++++++
target-arm/translate.c | 28 ----------------------------
2 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c002050..629095d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -61,6 +61,27 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf,
int reg)
return 0;
}
+static const ARMCPRegInfo cp_reginfo[] = {
+ /* DBGDIDR: just RAZ. In particular this means the "debug architecture
+ * version" bits will read as a reserved value, which should cause
+ * Linux to not try to use the debug hardware.
+ */
+ { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo v7_cp_reginfo[] = {
+ /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
+ * debug components
+ */
+ { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
+ .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
@@ -70,6 +91,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
return;
}
+ define_arm_cp_regs(cpu, cp_reginfo);
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ define_arm_cp_regs(cpu, v7_cp_reginfo);
+ }
}
ARMCPU *cpu_arm_init(const char *cpu_model)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 75e464d..d9fa431 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -6364,34 +6364,6 @@ static int disas_cp14_read(CPUARMState * env,
DisasContext *s, uint32_t insn)
int rt = (insn >> 12) & 0xf;
TCGv tmp;
- /* Minimal set of debug registers, since we don't support debug */
- if (op1 == 0 && crn == 0 && op2 == 0) {
- switch (crm) {
- case 0:
- /* DBGDIDR: just RAZ. In particular this means the
- * "debug architecture version" bits will read as
- * a reserved value, which should cause Linux to
- * not try to use the debug hardware.
- */
- tmp = tcg_const_i32(0);
- store_reg(s, rt, tmp);
- return 0;
- case 1:
- case 2:
- /* DBGDRAR and DBGDSAR: v7 only. Always RAZ since we
- * don't implement memory mapped debug components
- */
- if (ENABLE_ARCH_7) {
- tmp = tcg_const_i32(0);
- store_reg(s, rt, tmp);
- return 0;
- }
- break;
- default:
- break;
- }
- }
-
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
if (op1 == 6 && crn == 0 && crm == 0 && op2 == 0) {
/* TEECR */
--
1.7.1
- [Qemu-devel] [PATCH qom-next v2 29/33] target-arm: Convert final ID registers, (continued)
- [Qemu-devel] [PATCH qom-next v2 29/33] target-arm: Convert final ID registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 28/33] target-arm: Convert MPIDR, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 25/33] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 27/33] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 23/33] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 21/33] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 24/33] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registers to cp_reginfo,
Peter Maydell <=
- [Qemu-devel] [PATCH qom-next v2 12/33] target-arm: Convert performance monitor registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 01/33] target-arm: Fix 11MPCore cache type register value, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 03/33] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 02/33] target-arm: initial coprocessor register framework, Peter Maydell, 2012/05/14