[Qemu-devel] [PATCH 06/15] tcg-sparc: Support GUEST_BASE.

[Richard Henderson]

Signed-off-by: Richard Henderson <address@hidden>
---
 configure              |    2 ++
 tcg/sparc/tcg-target.c |   40 +++++++++++++++++++++++++++++-----------
 tcg/sparc/tcg-target.h |    2 ++
 3 files changed, 33 insertions(+), 11 deletions(-)

diff --git a/configure b/configure
index 7741ba9..a79a090 100755
--- a/configure
+++ b/configure
@@ -819,6 +819,7 @@ case "$cpu" in
            if test "$solaris" = "no" ; then
              QEMU_CFLAGS="-ffixed-g1 -ffixed-g6 $QEMU_CFLAGS"
            fi
+           host_guest_base="yes"
            ;;
     sparc64)
            LDFLAGS="-m64 $LDFLAGS"
@@ -827,6 +828,7 @@ case "$cpu" in
            if test "$solaris" != "no" ; then
              QEMU_CFLAGS="-ffixed-g1 $QEMU_CFLAGS"
            fi
+           host_guest_base="yes"
            ;;
     s390)
            QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS"
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 1b27626..9891648 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -59,6 +59,12 @@ static const char * const 
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 };
 #endif
 
+#ifdef CONFIG_USE_GUEST_BASE
+# define TCG_GUEST_BASE_REG TCG_REG_I3
+#else
+# define TCG_GUEST_BASE_REG TCG_REG_G0
+#endif
+
 #ifdef CONFIG_TCG_PASS_AREG0
 #define ARG_OFFSET 1
 #else
@@ -689,6 +695,14 @@ static void tcg_target_qemu_prologue(TCGContext *s)
     tcg_out32(s, SAVE | INSN_RD(TCG_REG_O6) | INSN_RS1(TCG_REG_O6) |
               INSN_IMM13(-(TCG_TARGET_STACK_MINFRAME +
                            CPU_TEMP_BUF_NLONGS * (int)sizeof(long))));
+
+#ifdef CONFIG_USE_GUEST_BASE
+    if (GUEST_BASE != 0) {
+        tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
+        tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+    }
+#endif
+
     tcg_out32(s, JMPL | INSN_RD(TCG_REG_G0) | INSN_RS1(TCG_REG_I1) |
               INSN_RS2(TCG_REG_G0));
     tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_I0);
@@ -819,8 +833,8 @@ static int tcg_out_tlb_load(TCGContext *s, int addrlo_idx, 
int mem_index,
 }
 #endif /* CONFIG_SOFTMMU */
 
-static void tcg_out_qemu_ld_direct(TCGContext *s, int addr, int datalo,
-                                   int datahi, int sizeop)
+static void tcg_out_qemu_ld_direct(TCGContext *s, int addr, int addend,
+                                   int datalo, int datahi, int sizeop)
 {
 #ifdef TARGET_WORDS_BIGENDIAN
     static const int ld_opc[8] = {
@@ -835,14 +849,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, int 
addr, int datalo,
     if (TCG_TARGET_REG_BITS == 32 && sizeop == 3) {
         /* Load all 64-bits into an O/G register.  */
         int reg64 = (datalo < 16 ? datalo : TCG_REG_O0);
-        tcg_out_ldst_rr(s, reg64, addr, TCG_REG_G0, ld_opc[sizeop]);
+        tcg_out_ldst_rr(s, reg64, addr, addend, ld_opc[sizeop]);
         /* Move the two 32-bit pieces into the destination registers.  */
         tcg_out_arithi(s, datahi, reg64, 32, SHIFT_SRLX);
         if (reg64 != datalo) {
             tcg_out_mov(s, TCG_TYPE_I32, datalo, reg64);
         }
     } else {
-        tcg_out_ldst_rr(s, datalo, addr, TCG_REG_G0, ld_opc[sizeop]);
+        tcg_out_ldst_rr(s, datalo, addr, addend, ld_opc[sizeop]);
     }
 }
 
@@ -869,7 +883,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg 
*args, int opc)
                                 label_ptr, offsetof(CPUTLBEntry, addr_read));
 
     /* TLB Hit.  */
-    tcg_out_qemu_ld_direct(s, addr_reg, datalo, datahi, opc);
+    tcg_out_qemu_ld_direct(s, addr_reg, TCG_REG_G0, datalo, datahi, opc);
 
     /* b,pt,n label1 */
     label_ptr[1] = (uint32_t *)s->code_ptr;
@@ -948,12 +962,14 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg 
*args, int opc)
         tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
         addr_reg = TCG_REG_I5;
     }
-    tcg_out_qemu_ld_direct(s, addr_reg, datalo, datahi, opc);
+    tcg_out_qemu_ld_direct(s, addr_reg,
+                           (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+                           datalo, datahi, opc);
 #endif /* CONFIG_SOFTMMU */
 }
 
-static void tcg_out_qemu_st_direct(TCGContext *s, int addr, int datalo,
-                                   int datahi, int sizeop)
+static void tcg_out_qemu_st_direct(TCGContext *s, int addr, int addend,
+                                   int datalo, int datahi, int sizeop)
 {
 #ifdef TARGET_WORDS_BIGENDIAN
     static const int st_opc[4] = { STB, STH, STW, STX };
@@ -967,7 +983,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, int addr, 
int datalo,
         tcg_out_arith(s, TCG_REG_O0, TCG_REG_O0, TCG_REG_O2, ARITH_OR);
         datalo = TCG_REG_O0;
     }
-    tcg_out_ldst_rr(s, datalo, addr, TCG_REG_G0, st_opc[sizeop]);
+    tcg_out_ldst_rr(s, datalo, addr, addend, st_opc[sizeop]);
 }
 
 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
@@ -992,7 +1008,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg 
*args, int opc)
                                 label_ptr, offsetof(CPUTLBEntry, addr_write));
 
     /* TLB Hit.  */
-    tcg_out_qemu_st_direct(s, addr_reg, datalo, datahi, opc);
+    tcg_out_qemu_st_direct(s, addr_reg, TCG_REG_G0, datalo, datahi, opc);
 
     /* b,pt,n label1 */
     label_ptr[1] = (uint32_t *)s->code_ptr;
@@ -1045,7 +1061,9 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg 
*args, int opc)
         tcg_out_arithi(s, TCG_REG_I5, addr_reg, 0, SHIFT_SRL);
         addr_reg = TCG_REG_I5;
     }
-    tcg_out_qemu_st_direct(s, addr_reg, datalo, datahi, opc);
+    tcg_out_qemu_st_direct(s, addr_reg,
+                           (GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_G0),
+                           datalo, datahi, opc);
 #endif /* CONFIG_SOFTMMU */
 }
 
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 56742bf..e69dfc8 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -126,6 +126,8 @@ typedef enum {
 #define TCG_TARGET_HAS_deposit_i64      0
 #endif
 
+#define TCG_TARGET_HAS_GUEST_BASE
+
 /* Note: must be synced with dyngen-exec.h */
 #ifdef CONFIG_SOLARIS
 #define TCG_AREG0 TCG_REG_G2
-- 
1.7.7.6