Re: [Qemu-devel] Support for Nested Paging

[Ankur Agrawal]

Hi,

Thanks for your reply.

I am a graduate student at Stony Brook University and am working on design and implementation of hypervisors for OSCAR lab (http://oscar.cs.stonybrook.edu/). Currently I am working on implementing emulation of Nested Page Tables in QEMU as present in AMD-V architectures. 

I would like to know if the QEMU team will be interested in having a patch which emulates the Nested Page Table and other hardware virtualization techniques supported by AMD-V or Intel-VT atchitectures. 

I would  love to help in maintenance of my patch or any other issues in the QEMU in future as well. 

I would also like to know if there is any chance that this can become a part of Google Summer of Code 2012.

Thanks,

Ankur

2012/3/3 陳韋任 <address@hidden>

> Does QEMU emulate the Nested Page Tables implemented by AMD-V architecture or the Intel VT?

 I think the answer is no.

> Also I am trying to understand the QEMU source with an objective of participating in the Google Summer of Code and contributing to QEMU. I have tried tracing through the code but seems this link http://repo.or.cz/w/qemu/stefanha.git/blob_plain/refs/heads/tracing:/docs/tracing.txt is not updated because many of the options do not work here. I would very happy if someone could provide me links to a good starting point to understand QEMU source code.

 The "tracing" you mentioned is not tend to help reading the code. Depends on
which part of QEMU you're trying to play with, you have some background
knowledge of it. See "Getting to know the code" on the QEMU wiki [1]. And the
slides mentioned on the mail below is a good start.

 http://www.mail-archive.com/address@hidden/msg99864.html

HTH,
chenwj

[1] http://wiki.qemu.org/Documentation/GettingStartedDevelopers#Getting_to_know_the_code

--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj