Re: [Qemu-devel] [PATCH] pci: set memory type for memory behind the bridge

[Alexander Graf]

On 02/21/2012 02:57 PM, Michael S. Tsirkin wrote:
> As we make upper bits in IO and prefetcheable memory
> registers writeable, we should declare support
> for 64 bit prefetcheable memory and 32 bit io
> in the bridge.
>
> This changes the default for apb, dec, but I'm guessing
> they got the defaults wrong by accident.
> Alternatively, we could let bridges declare lack of
> 64 bit support and make the upper bits read-only zero.
>
> With this applied, we can drop these bits
> from express code.

Ben, you know these devices better than us. Any comments? :)


Alex

> Reported-by: Gerd Hoffmann<address@hidden>
> Signed-off-by: Michael S. Tsirkin<address@hidden>
>
> Could someone familiar with apb,dec ack this please?
>
> ---
>   hw/pci.c |   15 +++++++++++++--
>   1 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index 31d6a5f..3ca5f4c 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -611,7 +611,7 @@ static void pci_init_w1cmask(PCIDevice *dev)
>                    PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
>   }
>
> -static void pci_init_wmask_bridge(PCIDevice *d)
> +static void pci_init_mask_bridge(PCIDevice *d)
>   {
>       /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
>          PCI_SEC_LETENCY_TIMER */
> @@ -632,6 +632,14 @@ static void pci_init_wmask_bridge(PCIDevice *d)
>       /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
>       memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
>
> +    /* Supported memory and i/o types */
> +    d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32;
> +    d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32;
> +    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
> +                               PCI_PREF_RANGE_TYPE_64);
> +    pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
> +                               PCI_PREF_RANGE_TYPE_64);
> +
>   /* TODO: add this define to pci_regs.h in linux and then in qemu. */
>   #define  PCI_BRIDGE_CTL_VGA_16BIT     0x10    /* VGA 16-bit decode */
>   #define  PCI_BRIDGE_CTL_DISCARD               0x100   /* Primary discard 
> timer */
> @@ -654,6 +662,9 @@ static void pci_init_wmask_bridge(PCIDevice *d)
>        * completeness. */
>       pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
>                    PCI_BRIDGE_CTL_DISCARD_STATUS);
> +    d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
> +    pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
> +                               PCI_PREF_RANGE_TYPE_MASK);
>   }
>
>   static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
> @@ -775,7 +786,7 @@ static PCIDevice *do_pci_register_device(PCIDevice 
> *pci_dev, PCIBus *bus,
>       pci_init_wmask(pci_dev);
>       pci_init_w1cmask(pci_dev);
>       if (pc->is_bridge) {
> -        pci_init_wmask_bridge(pci_dev);
> +        pci_init_mask_bridge(pci_dev);
>       }
>       if (pci_init_multifunction(bus, pci_dev)) {
>           pci_config_free(pci_dev);