[Qemu-devel] [PATCH RFC v3 11/21] target-arm: Store cp15 c0_cachetype register in ARMCPUClass

[Andreas Färber]

Signed-off-by: Andreas Färber <address@hidden>
Cc: Peter Maydell <address@hidden>
---
 target-arm/cpu-core.h |    1 +
 target-arm/cpu.c      |   18 ++++++++++++++++++
 target-arm/helper.c   |   12 ------------
 3 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/target-arm/cpu-core.h b/target-arm/cpu-core.h
index bb59f8d..1d5adc8 100644
--- a/target-arm/cpu-core.h
+++ b/target-arm/cpu-core.h
@@ -43,6 +43,7 @@ typedef struct ARMCPUClass {
 
     struct {
         uint32_t c0_cpuid;
+        uint32_t c0_cachetype;
         uint32_t c0_c1[8];
         uint32_t c0_c2[8];
     } cp15;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 909eb1a..fe34b31 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -46,6 +46,7 @@ static void arm_cpu_reset(CPU *c)
     env->cp15.c15_config_base_address = tmp;
 
     /* TODO Move these into arm_cpu_initfn() once no longer zeroed above. */
+    env->cp15.c0_cachetype = cpu_class->cp15.c0_cachetype;
     memcpy(env->cp15.c0_c1, cpu_class->cp15.c0_c1, 8 * sizeof(uint32_t));
     memcpy(env->cp15.c0_c2, cpu_class->cp15.c0_c2, 8 * sizeof(uint32_t));
 
@@ -164,6 +165,7 @@ static inline void unset_class_feature(ARMCPUClass *klass, 
int feature)
 typedef struct ARMCPUInfo {
     const char *name;
     uint32_t id;
+    uint32_t cp15_c0_cachetype;
     uint32_t cp15_c0_c1[8];
     uint32_t cp15_c0_c2[8];
     uint32_t features;
@@ -183,6 +185,7 @@ static void arm1136_r0_class_init(ARMCPUClass *k, const 
ARMCPUInfo *info)
      * for 1136_r2 (in particular r0p2 does not actually implement most
      * of the ID registers).
      */
+    k->cp15.c0_cachetype = r1_class->cp15.c0_cachetype;
     memcpy(k->cp15.c0_c1, r1_class->cp15.c0_c1, 8 * sizeof(uint32_t));
     memcpy(k->cp15.c0_c2, r1_class->cp15.c0_c2, 8 * sizeof(uint32_t));
 }
@@ -211,12 +214,16 @@ static void sa11xx_class_init(ARMCPUClass *k, const 
ARMCPUInfo *info)
 
 static void pxa25x_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 {
+    k->cp15.c0_cachetype = 0xd172172;
+
     set_class_feature(k, ARM_FEATURE_V5);
     set_class_feature(k, ARM_FEATURE_XSCALE);
 }
 
 static void pxa270_class_init(ARMCPUClass *k, const ARMCPUInfo *info)
 {
+    k->cp15.c0_cachetype = 0xd172172;
+
     set_class_feature(k, ARM_FEATURE_V5);
     set_class_feature(k, ARM_FEATURE_XSCALE);
     set_class_feature(k, ARM_FEATURE_IWMMXT);
@@ -226,18 +233,21 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "arm926",
         .id = 0x41069265,
+        .cp15_c0_cachetype = 0x1dd20d2,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(VFP),
     },
     {
         .name = "arm946",
         .id = 0x41059461,
+        .cp15_c0_cachetype = 0x0f004006,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(MPU),
     },
     {
         .name = "arm1026",
         .id = 0x4106a262,
+        .cp15_c0_cachetype = 0x1dd20d2,
         .features = ARM_FEATURE(V5) |
                     ARM_FEATURE(VFP) |
                     ARM_FEATURE(AUXCR),
@@ -254,6 +264,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "arm1136",
         .id = 0x4117b363,
+        .cp15_c0_cachetype = 0x1dd20d2,
         .cp15_c0_c1 = {
             0x111, 0x1, 0x2, 0x3,
             0x01130003, 0x10030302, 0x01222110, 0
@@ -268,6 +279,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "arm1176",
         .id = 0x410fb767,
+        .cp15_c0_cachetype = 0x1dd20d2,
         .cp15_c0_c1 = {
             0x111, 0x11, 0x33, 0,
             0x01130003, 0x10030302, 0x01222100, 0
@@ -283,6 +295,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "arm11mpcore",
         .id = 0x410fb022,
+        .cp15_c0_cachetype = 0x1dd20d2,
         .cp15_c0_c1 = {
             0x111, 0x1, 0, 0x2,
             0x01100103, 0x10020302, 0x01222000, 0
@@ -304,6 +317,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "cortex-a8",
         .id = 0x410fc080,
+        .cp15_c0_cachetype = 0x82048004,
         .cp15_c0_c1 = {
             0x1031, 0x11, 0x400, 0,
             0x31100003, 0x20000000, 0x01202000, 0x11
@@ -320,6 +334,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "cortex-a9",
         .id = 0x410fc090,
+        .cp15_c0_cachetype = 0x80038003,
         .cp15_c0_c1 = {
             0x1031, 0x11, 0x000, 0,
             0x00100103, 0x20000000, 0x01230000, 0x00002111
@@ -342,6 +357,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "cortex-a15",
         .id = 0x412fc0f1,
+        .cp15_c0_cachetype = 0x8444c004,
         .cp15_c0_c1 = {
             0x00001131, 0x00011011, 0x02010555, 0x00000000,
             0x10201105, 0x20000000, 0x01240000, 0x02102211
@@ -362,6 +378,7 @@ static const ARMCPUInfo arm_cpus[] = {
     {
         .name = "ti925t",
         .id = 0x54029252,
+        .cp15_c0_cachetype = 0x5109149,
         .features = ARM_FEATURE(V4T) |
                     ARM_FEATURE(OMAPCP),
         .class_init = ti925t_class_init,
@@ -467,6 +484,7 @@ static void arm_cpu_class_init(ObjectClass *klass, void 
*data)
     cpu_class->reset = arm_cpu_reset;
 
     k->cp15.c0_cpuid = info->id;
+    k->cp15.c0_cachetype = info->cp15_c0_cachetype;
     memcpy(k->cp15.c0_c1, info->cp15_c0_c1, 8 * sizeof(uint32_t));
     memcpy(k->cp15.c0_c2, info->cp15_c0_c2, 8 * sizeof(uint32_t));
     k->features = info->features;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2af8df4..9a4afad 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -15,16 +15,13 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t 
id)
     switch (id) {
     case ARM_CPUID_ARM926:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
-        env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00090078;
         break;
     case ARM_CPUID_ARM946:
-        env->cp15.c0_cachetype = 0x0f004006;
         env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_ARM1026:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
-        env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00090078;
         break;
     case ARM_CPUID_ARM1136:
@@ -42,27 +39,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t 
id)
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
-        env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM1176:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b5;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
-        env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM11MPCORE:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
-        env->cp15.c0_cachetype = 0x1dd20d2;
         break;
     case ARM_CPUID_CORTEXA8:
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
-        env->cp15.c0_cachetype = 0x82048004;
         env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
         env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
         env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
@@ -73,7 +66,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->vfp.xregs[ARM_VFP_FPSID] = 0x41034000; /* Guess */
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
-        env->cp15.c0_cachetype = 0x80038003;
         env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
         env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
         env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
@@ -83,7 +75,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410430f0;
         env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
         env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
-        env->cp15.c0_cachetype = 0x8444c004;
         env->cp15.c0_clid = 0x0a200023;
         env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
         env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
@@ -92,7 +83,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         break;
     case ARM_CPUID_TI915T:
     case ARM_CPUID_TI925T:
-        env->cp15.c0_cachetype = 0x5109149;
         env->cp15.c1_sys = 0x00000070;
         env->cp15.c15_i_max = 0x000;
         env->cp15.c15_i_min = 0xff0;
@@ -103,7 +93,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
     case ARM_CPUID_PXA261:
     case ARM_CPUID_PXA262:
         /* JTAG_ID is ((id << 28) | 0x09265013) */
-        env->cp15.c0_cachetype = 0xd172172;
         env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_PXA270_A0:
@@ -114,7 +103,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t 
id)
     case ARM_CPUID_PXA270_C5:
         /* JTAG_ID is ((id << 28) | 0x09265013) */
         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
-        env->cp15.c0_cachetype = 0xd172172;
         env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_SA1100:
-- 
1.7.7