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Re: [Qemu-devel] [Android-virt] [PATCH 00/12] Add support for Cortex-A15
From: |
Marc Zyngier |
Subject: |
Re: [Qemu-devel] [Android-virt] [PATCH 00/12] Add support for Cortex-A15 and vexpress-a15 |
Date: |
Fri, 27 Jan 2012 10:28:45 +0000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:9.0) Gecko/20111220 Thunderbird/9.0 |
On 17/01/12 19:08, Peter Maydell wrote:
> On 15 January 2012 22:56, Christoffer Dall <address@hidden> wrote:
>> On Fri, Jan 13, 2012 at 3:57 PM, Peter Maydell <address@hidden> wrote:
>>> PPS: these patches are against qemu-master so for kvm you'd need
>>> to (a) rebase them on qemu-linaro (b) put the kvm patches on top
>>> of these (c) wait for me to do a. for you ;-)
>>
>> ok, I'll test this with the most recent KVM changes soon and also look
>> forward for your merge... :)
>
> vexpress-a15 now in qemu-linaro git tree. However it doesn't boot under
> KVM:
>
> address@hidden:~# /usr/local/bin/qemu-system-arm -enable-kvm
> -kernel /a15-no-lpae-uImage -m 128 -serial stdio -drive
> if=sd,file=/maz/vex
> press.img -M vexpress-a15 -display none -append "console=ttyAMA0
> earlyprintk rootwait mem=128M root=/dev/mmcblk0p2 rw --debug"
> Uncompressing Linux... done, booting the kernel.
> Booting Linux on physical CPU 0
> Linux version 3.1.0+ (address@hidden) (gcc version 4.6.1
> (Ubuntu/Linaro 4.6.1-9ubuntu3) ) #19 SMP Fri Jan 13 12:23:22 GMT 2012
> CPU: ARMv7 Processor [412fc0f1] revision 1 (ARMv7), cr=10c5387f
> CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
> Machine: ARM-Versatile Express
> SoC: ARM VE Platform
> bootconsole [earlycon0] enabled
> Memory policy: ECC disabled, Data cache writealloc
> error: kvm run failed Invalid argument
> Aborted
>
> Under TCG the next thing printed is
> ct_ca15x4_init_cpu_map: ncores 1
> Architected timer frequency not available
> sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
>
> ...possibly the kernel side needs to implement the A15 L2 cache control
> register, which is where the guest kernel picks up the number of cores
> from; see patch 10 for the TCG version.
I've pushed a new branch (kvm-v3.3-rc1) to my arm-platforms repo. It
contains a fix (or shall we call it a horrible hack?) for the above.
M.
--
Jazz is not dead. It just smells funny...
- Re: [Qemu-devel] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop, (continued)
- [Qemu-devel] [PATCH 08/12] hw/a15mpcore.c: Add Cortex-A15 private peripheral model, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 01/12] vexpress, realview: Add (dummy) L2 cache controller, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 07/12] hw/vexpress.c: Instantiate the motherboard CLCD, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 12/12] hw/vexpress.c: Add vexpress-a15 machine, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 05/12] hw/vexpress.c: Move secondary CPU boot code to SRAM, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 11/12] arm_boot: Pass base address of GIC CPU interface, not whole GIC, Peter Maydell, 2012/01/13
- Re: [Qemu-devel] [PATCH 00/12] Add support for Cortex-A15 and vexpress-a15, Peter Maydell, 2012/01/13