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[Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only |
Date: |
Wed, 25 Jan 2012 15:27:42 +0000 |
In the helper routines for VCVT float-to-int conversions, add
an explicit cast rather than relying on the softfloat int32
type being exactly 32 bits wide (which it is not guaranteed to be).
Without this, if the softfloat type was 64 bits wide we would
get zero-extension of the 32 bit value from the ARM register
rather than sign-extension, since TCG i32 values are passed as
uint32_t.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f11279e..f6e998b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2785,7 +2785,7 @@ DO_VFP_cmp(d, float64)
float##fsz HELPER(name)(uint32_t x, void *fpstp) \
{ \
float_status *fpst = fpstp; \
- return sign##int32_to_##float##fsz(x, fpst); \
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
}
#define CONV_FTOI(name, fsz, sign, round) \
--
1.7.1
- [Qemu-devel] [PULL 0/5] target-arm queue, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only,
Peter Maydell <=
- [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers, Peter Maydell, 2012/01/25
- [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition, Peter Maydell, 2012/01/25
- Re: [Qemu-devel] [PULL 0/5] target-arm queue, Blue Swirl, 2012/01/28