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Re: [Qemu-devel] [Android-virt] [PATCH 03/12] hw/arm_boot.c: Make SMP bo
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [Android-virt] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop |
Date: |
Mon, 16 Jan 2012 08:31:34 +0000 |
On 16 January 2012 01:56, Alexander Graf <address@hidden> wrote:
>
> On 13.01.2012, at 21:52, Peter Maydell wrote:
>
>> From: Evgeny Voevodin <address@hidden>
>>
>> The secondary CPU bootloader in arm_boot.c holds secondary CPUs in a
>> pen until the primary CPU releases them. Make boards specify the
>> address to be polled to determine whether to leave the pen (it was
>> previously hardcoded to 0x10000030, which is a Versatile Express/
>> Realview specific system register address).
>
> Is smp_boot implementing the same logic as hw/ppce500_spin.c? It
> looks like the normal u-boot way of waiting for a magic address
> to be written with boot info. What I don't understand is the WFI.
> How can you wait for an interrupt if the trigger is a memory
> write? Or are you actually getting IPIs?
Basically this code is implementing the boot-rom half of
what is technically a platform-specific contract[*] between
the boot rom and the Linux kernel. The kernel end has to
(a) write the secondary CPU's entry point into the register
being polled and (b) send the CPU a softirq (an IPI, in
other words). The WFI basically allows h/w to avoid running
3 cores at 100% when we're booting a uniprocessor OS.
So the arm_boot end has to (a) enable the CPU's interrupt
controller, (b) wait for interrupt, (c) get the entry point
and jump to it.
[*] realview, vexpress, highbank and exynos4 all do something
that's sufficiently similar that we can handle them all by
parameterising the secondary boot code a bit. omap is kinda
different but then we don't support -kernel with omap anyway.
-- PMM
- [Qemu-devel] [PATCH 00/12] Add support for Cortex-A15 and vexpress-a15, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 09/12] Add dummy implementation of generic timer cp15 registers, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 10/12] Add Cortex-A15 CPU definition, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 04/12] hw/vexpress.c: Make motherboard peripheral memory map table-driven, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 02/12] arm: make the number of GIC interrupts configurable, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 06/12] hw/vexpress.c: Factor out daughterboard-specific initialization, Peter Maydell, 2012/01/13
- [Qemu-devel] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop, Peter Maydell, 2012/01/13
- Re: [Qemu-devel] [PATCH 03/12] hw/arm_boot.c: Make SMP boards specify address to poll in bootup loop, andrzej zaborowski, 2012/01/16
[Qemu-devel] [PATCH 08/12] hw/a15mpcore.c: Add Cortex-A15 private peripheral model, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 01/12] vexpress, realview: Add (dummy) L2 cache controller, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 07/12] hw/vexpress.c: Instantiate the motherboard CLCD, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 12/12] hw/vexpress.c: Add vexpress-a15 machine, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 05/12] hw/vexpress.c: Move secondary CPU boot code to SRAM, Peter Maydell, 2012/01/13
[Qemu-devel] [PATCH 11/12] arm_boot: Pass base address of GIC CPU interface, not whole GIC, Peter Maydell, 2012/01/13
Re: [Qemu-devel] [PATCH 00/12] Add support for Cortex-A15 and vexpress-a15, Peter Maydell, 2012/01/13