[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v4 3/7] arm: add dummy v7 cp15 config_base_register
From: |
Mark Langsdorf |
Subject: |
[Qemu-devel] [PATCH v4 3/7] arm: add dummy v7 cp15 config_base_register |
Date: |
Tue, 27 Dec 2011 19:24:36 -0600 |
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.
Signed-off-by: Mark Langsdorf <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
Changes from v3
None
Changes from v2
Added test against op2
Changes from v1
renamed the register
added comments about how it will change when QOM CPUs are added
target-arm/cpu.h | 1 +
target-arm/helper.c | 14 ++++++++++++++
2 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4d742f..449e620 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -149,6 +149,7 @@ typedef struct CPUARMState {
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
uint32_t c15_threadid; /* TI debugger thread-ID. */
+ uint32_t c15_config_base_address; /* SCU base address. */
} cp15;
struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..b235fed 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
* 0x200 << ($rn & 0xfff), when MMU is off. */
goto bad_reg;
}
+ if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+ switch (crm) {
+ case 0:
+ /* The config_base_address should hold the value of
+ * the peripheral base. ARM should get this from a CPU
+ * object property, but that support isn't available in
+ * December 2011. Default to 0 for now and board models
+ * that care can set it by a private hook */
+ if ((op1 == 4) && (op2 == 0)) {
+ return env->cp15.c15_config_base_address;
+ }
+ }
+ goto bad_reg;
+ }
return 0;
}
bad_reg:
--
1.7.5.4
- [Qemu-devel] [PATCH v4 0/7] various ARM fixes, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 4/7] arm: add dummy gic security registers, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 1/7] arm: add missing scu registers, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 3/7] arm: add dummy v7 cp15 config_base_register,
Mark Langsdorf <=
- [Qemu-devel] [PATCH v4 5/7] add L2x0/PL310 cache controller device, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 6/7] Add xgmac ethernet model, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 2/7] arm: Set frequencies for arm_timer, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 7/7] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2011/12/27