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Re: [Qemu-devel] [PATCH 3/9] arm: add missing v7 cp15 registers

From: Peter Maydell
Subject: Re: [Qemu-devel] [PATCH 3/9] arm: add missing v7 cp15 registers
Date: Wed, 21 Dec 2011 21:10:25 +0000

On 21 December 2011 16:37, Mark Langsdorf <address@hidden> wrote:
> On 12/20/2011 01:48 PM, Peter Maydell wrote:
>> This commit leaves the register with a reset value of 0, which
>> isn't right (we only implement A9MP, not A9UP, so the reset value
>> should be settable by the board at init time somehow depending
>> where the a9mpcore_priv device is mapped. Not sure what the
>> cleanest way to do that is.)
> I can add a DEFINE_PROP_UINT32 to a9mpcore_priv, which would give
> anyone who wants to set the property an easy way to do so. I'm
> not sure how to hook the a9mpcore_priv to the CPUARMState, though.
> They don't appear to reference each other.

Yes, we don't really model the private peripherals very sensibly:
they should be an integral part of the CPU but for historical
reasons they've been done as a totally separate device. I don't
think a property is the right thing, though -- ideally the a9mpcore
device should be able to find out for itself where it was mapped.

Avi: is there a way for a device (sysbus device in this case) to
find out for one of its memory regions where it has been mapped
in the address space? The context here is that the Cortex-A9
has a cp15 register whose value is "base address of the private
peripherals", and it would be nice not to have to have boards
saying both "map mmio region at X" and "set property so register
reads as X"... [You could argue that hardware implementations
have to do the equivalent of both of these things separately,
I suppose, but it's still not very pretty.]

-- PMM

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