[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH for v1.0 1/3] msix: track function masked in pci dev
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PATCH for v1.0 1/3] msix: track function masked in pci device state |
Date: |
Mon, 21 Nov 2011 18:57:21 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
Only go over the table when function is masked.
This is not really important for qemu.git but helps
fix a bug in qemu-kvm.git.
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/msix.c | 21 ++++++++++++++-------
hw/pci.h | 2 ++
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/hw/msix.c b/hw/msix.c
index b15bafc..63b41b9 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -79,6 +79,7 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned
short nentries,
/* Make flags bit writable. */
pdev->wmask[config_offset + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
MSIX_MASKALL_MASK;
+ pdev->msix_function_masked = true;
return 0;
}
@@ -117,16 +118,11 @@ static void msix_clr_pending(PCIDevice *dev, int vector)
*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
}
-static int msix_function_masked(PCIDevice *dev)
-{
- return dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
MSIX_MASKALL_MASK;
-}
-
static int msix_is_masked(PCIDevice *dev, int vector)
{
unsigned offset =
vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
- return msix_function_masked(dev) ||
+ return dev->msix_function_masked ||
dev->msix_table_page[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
}
@@ -138,24 +134,34 @@ static void msix_handle_mask_update(PCIDevice *dev, int
vector)
}
}
+static void msix_update_function_masked(PCIDevice *dev)
+{
+ dev->msix_function_masked = !msix_enabled(dev) ||
+ (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
+}
+
/* Handle MSI-X capability config write. */
void msix_write_config(PCIDevice *dev, uint32_t addr,
uint32_t val, int len)
{
unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
int vector;
+ bool was_masked;
if (!range_covers_byte(addr, len, enable_pos)) {
return;
}
+ was_masked = dev->msix_function_masked;
+ msix_update_function_masked(dev);
+
if (!msix_enabled(dev)) {
return;
}
pci_device_deassert_intx(dev);
- if (msix_function_masked(dev)) {
+ if (dev->msix_function_masked == was_masked) {
return;
}
@@ -300,6 +306,7 @@ void msix_load(PCIDevice *dev, QEMUFile *f)
msix_free_irq_entries(dev);
qemu_get_buffer(f, dev->msix_table_page, n * PCI_MSIX_ENTRY_SIZE);
qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
+ msix_update_function_masked(dev);
}
/* Does device support MSI-X? */
diff --git a/hw/pci.h b/hw/pci.h
index 4b2e785..625e717 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -178,6 +178,8 @@ struct PCIDevice {
unsigned *msix_entry_used;
/* Region including the MSI-X table */
uint32_t msix_bar_size;
+ /* MSIX function mask set or MSIX disabled */
+ bool msix_function_masked;
/* Version id needed for VMState */
int32_t version_id;
--
1.7.5.53.gc233e