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Re: [Qemu-devel] [PATCH] arm_gic: handle banked enable bits for per-cpu
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH] arm_gic: handle banked enable bits for per-cpu interrupts |
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Date: |
Tue, 1 Nov 2011 22:42:14 +0000 |
On 1 November 2011 22:31, Peter Maydell <address@hidden> wrote:
> On 28 October 2011 18:40, Rabin Vincent <address@hidden> wrote:
>> The first enable set/clear register (which controls the PPIs and SGIs)
>> is supposed to be banked for each processor. Currently it is just
>> handled globally and this prevents recent SMP Linux kernels from
>> booting, because CPU0 stops receiving localtimer interrupts when CPU1
>> disables them locally.
> Reviewed-by: Peter Maydell <address@hidden>
This has just missed the 1.0rc0 deadline but as it's a bug fix
we can put it into rc1.
-- PMM