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[Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when possible. |
|
Date: |
Wed, 26 Oct 2011 14:15:25 -0700 |
This also removes the unused ENV parameter from these helpers.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/fop_helper.c | 2 +-
target-sparc/helper.h | 50 +++++++++++++++------------
target-sparc/translate.c | 83 ++++++++++++++++++---------------------------
target-sparc/vis_helper.c | 35 +++++++++----------
4 files changed, 78 insertions(+), 92 deletions(-)
diff --git a/target-sparc/fop_helper.c b/target-sparc/fop_helper.c
index f6348c2..e652021 100644
--- a/target-sparc/fop_helper.c
+++ b/target-sparc/fop_helper.c
@@ -182,7 +182,7 @@ float32 helper_fabss(float32 src)
}
#ifdef TARGET_SPARC64
-float64 helper_fabsd(CPUState *env, float64 src)
+float64 helper_fabsd(float64 src)
{
return float64_abs(src);
}
diff --git a/target-sparc/helper.h b/target-sparc/helper.h
index 86fad6e..ba0ad81 100644
--- a/target-sparc/helper.h
+++ b/target-sparc/helper.h
@@ -16,7 +16,7 @@ DEF_HELPER_1(rdccr, tl, env)
DEF_HELPER_2(wrccr, void, env, tl)
DEF_HELPER_1(rdcwp, tl, env)
DEF_HELPER_2(wrcwp, void, env, tl)
-DEF_HELPER_3(array8, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(array8, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
DEF_HELPER_3(alignaddr, tl, env, tl, tl)
DEF_HELPER_1(popc, tl, tl)
DEF_HELPER_3(ldda_asi, void, tl, int, int)
@@ -48,7 +48,7 @@ DEF_HELPER_4(st_asi, void, tl, i64, int, int)
DEF_HELPER_2(ldfsr, void, env, i32)
DEF_HELPER_1(check_ieee_exceptions, void, env)
DEF_HELPER_1(clear_float_exceptions, void, env)
-DEF_HELPER_1(fabss, f32, f32)
+DEF_HELPER_FLAGS_1(fabss, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
DEF_HELPER_2(fsqrts, f32, env, f32)
DEF_HELPER_2(fsqrtd, f64, env, f64)
DEF_HELPER_3(fcmps, void, env, f32, f32)
@@ -60,7 +60,7 @@ DEF_HELPER_1(fcmpq, void, env)
DEF_HELPER_1(fcmpeq, void, env)
#ifdef TARGET_SPARC64
DEF_HELPER_2(ldxfsr, void, env, i64)
-DEF_HELPER_2(fabsd, f64, env, f64)
+DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_CONST | TCG_CALL_PURE, f64, f64)
DEF_HELPER_3(fcmps_fcc1, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc2, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc3, void, env, f32, f32)
@@ -102,14 +102,14 @@ DEF_HELPER_3(fdivs, f32, env, f32, f32)
DEF_HELPER_3(fsmuld, f64, env, f32, f32)
DEF_HELPER_3(fdmulq, void, env, f64, f64);
-DEF_HELPER_1(fnegs, f32, f32)
+DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_CONST | TCG_CALL_PURE, f32, f32)
DEF_HELPER_2(fitod, f64, env, s32)
DEF_HELPER_2(fitoq, void, env, s32)
DEF_HELPER_2(fitos, f32, env, s32)
#ifdef TARGET_SPARC64
-DEF_HELPER_1(fnegd, f64, f64)
+DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_CONST | TCG_CALL_PURE, f64, f64)
DEF_HELPER_1(fnegq, void, env)
DEF_HELPER_2(fxtos, f32, env, s64)
DEF_HELPER_2(fxtod, f64, env, s64)
@@ -130,26 +130,32 @@ DEF_HELPER_2(fdtox, s64, env, f64)
DEF_HELPER_1(fqtox, s64, env)
DEF_HELPER_3(faligndata, i64, env, i64, i64)
-DEF_HELPER_3(fpmerge, i64, env, i64, i64)
-DEF_HELPER_3(fmul8x16, i64, env, i64, i64)
-DEF_HELPER_3(fmul8x16al, i64, env, i64, i64)
-DEF_HELPER_3(fmul8x16au, i64, env, i64, i64)
-DEF_HELPER_3(fmul8sux16, i64, env, i64, i64)
-DEF_HELPER_3(fmul8ulx16, i64, env, i64, i64)
-DEF_HELPER_3(fmuld8sux16, i64, env, i64, i64)
-DEF_HELPER_3(fmuld8ulx16, i64, env, i64, i64)
-DEF_HELPER_3(fexpand, i64, env, i64, i64)
-#define VIS_HELPER(name) \
- DEF_HELPER_3(f ## name ## 16, i64, env, i64, i64) \
- DEF_HELPER_3(f ## name ## 16s, i32, env, i32, i32) \
- DEF_HELPER_3(f ## name ## 32, i64, env, i64, i64) \
- DEF_HELPER_3(f ## name ## 32s, i32, env, i32, i32)
+DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmul8x16al, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmul8x16au, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmul8sux16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmul8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmuld8sux16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fmuld8ulx16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+DEF_HELPER_FLAGS_2(fexpand, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64)
+#define VIS_HELPER(name) \
+ DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i64, i64, i64) \
+ DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i32, i32, i32) \
+ DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i64, i64, i64) \
+ DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i32, i32, i32)
VIS_HELPER(padd);
VIS_HELPER(psub);
-#define VIS_CMPHELPER(name) \
- DEF_HELPER_3(f##name##16, i64, env, i64, i64) \
- DEF_HELPER_3(f##name##32, i64, env, i64, i64)
+#define VIS_CMPHELPER(name) \
+ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i64, i64, i64) \
+ DEF_HELPER_FLAGS_2(f##name##32, TCG_CALL_CONST | TCG_CALL_PURE, \
+ i64, i64, i64)
VIS_CMPHELPER(cmpgt);
VIS_CMPHELPER(cmpeq);
VIS_CMPHELPER(cmple);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index f41ef98..80f0058 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2722,7 +2722,7 @@ static void disas_sparc_insn(DisasContext * dc)
case 0xa: /* V9 fabsd */
cpu_src1_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fabsd(cpu_dst_64, cpu_env, cpu_src1_64);
+ gen_helper_fabsd(cpu_dst_64, cpu_src1_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0xb: /* V9 fabsq */
@@ -3902,14 +3902,14 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
- gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
+ gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x012: /* VIS I array16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
- gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
+ gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
gen_movl_TN_reg(rd, cpu_dst);
break;
@@ -3917,7 +3917,7 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1 = get_src1(insn, cpu_src1);
gen_movl_reg_TN(rs2, cpu_src2);
- gen_helper_array8(cpu_dst, cpu_env, cpu_src1, cpu_src2);
+ gen_helper_array8(cpu_dst, cpu_src1, cpu_src2);
tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
gen_movl_TN_reg(rd, cpu_dst);
break;
@@ -3936,64 +3936,56 @@ static void disas_sparc_insn(DisasContext * dc)
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmple16(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x022: /* VIS I fcmpne16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpne16(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x024: /* VIS I fcmple32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmple32(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x026: /* VIS I fcmpne32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpne32(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x028: /* VIS I fcmpgt16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpgt16(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x02a: /* VIS I fcmpeq16 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpeq16(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x02c: /* VIS I fcmpgt32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpgt32(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x02e: /* VIS I fcmpeq32 */
CHECK_FPU_FEATURE(dc, VIS1);
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
- gen_helper_fcmpeq32(cpu_dst, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64);
gen_movl_TN_reg(rd, cpu_dst);
break;
case 0x031: /* VIS I fmul8x16 */
@@ -4001,8 +3993,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmul8x16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmul8x16(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x033: /* VIS I fmul8x16au */
@@ -4010,8 +4001,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmul8x16au(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmul8x16au(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x035: /* VIS I fmul8x16al */
@@ -4019,8 +4010,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmul8x16al(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmul8x16al(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x036: /* VIS I fmul8sux16 */
@@ -4028,8 +4019,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmul8sux16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmul8sux16(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x037: /* VIS I fmul8ulx16 */
@@ -4037,8 +4028,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmul8ulx16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmul8ulx16(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x038: /* VIS I fmuld8sux16 */
@@ -4046,8 +4037,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmuld8sux16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmuld8sux16(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x039: /* VIS I fmuld8ulx16 */
@@ -4055,8 +4046,8 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fmuld8ulx16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fmuld8ulx16(cpu_dst_64, cpu_src1_64,
+ cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x03a: /* VIS I fpack32 */
@@ -4079,8 +4070,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fpmerge(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fpmerge(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x04c: /* VIS II bshuffle */
@@ -4091,8 +4081,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fexpand(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fexpand(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x050: /* VIS I fpadd16 */
@@ -4100,8 +4089,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fpadd16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fpadd16(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x051: /* VIS I fpadd16s */
@@ -4109,8 +4097,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_32 = gen_load_fpr_F(dc, rs1);
cpu_src2_32 = gen_load_fpr_F(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F();
- gen_helper_fpadd16s(cpu_dst_32, cpu_env,
- cpu_src1_32, cpu_src2_32);
+ gen_helper_fpadd16s(cpu_dst_32, cpu_src1_32, cpu_src2_32);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x052: /* VIS I fpadd32 */
@@ -4118,8 +4105,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fpadd32(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fpadd32(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x053: /* VIS I fpadd32s */
@@ -4135,8 +4121,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fpsub16(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fpsub16(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x055: /* VIS I fpsub16s */
@@ -4144,8 +4129,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_32 = gen_load_fpr_F(dc, rs1);
cpu_src2_32 = gen_load_fpr_F(dc, rs2);
cpu_dst_32 = gen_dest_fpr_F();
- gen_helper_fpsub16s(cpu_dst_32, cpu_env,
- cpu_src1_32, cpu_src2_32);
+ gen_helper_fpsub16s(cpu_dst_32, cpu_src1_32, cpu_src2_32);
gen_store_fpr_F(dc, rd, cpu_dst_32);
break;
case 0x056: /* VIS I fpsub32 */
@@ -4153,8 +4137,7 @@ static void disas_sparc_insn(DisasContext * dc)
cpu_src1_64 = gen_load_fpr_D(dc, rs1);
cpu_src2_64 = gen_load_fpr_D(dc, rs2);
cpu_dst_64 = gen_dest_fpr_D();
- gen_helper_fpsub32(cpu_dst_64, cpu_env,
- cpu_src1_64, cpu_src2_64);
+ gen_helper_fpsub32(cpu_dst_64, cpu_src1_64, cpu_src2_64);
gen_store_fpr_D(dc, rd, cpu_dst_64);
break;
case 0x057: /* VIS I fpsub32s */
diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c
index a007b0f..39c8d9a 100644
--- a/target-sparc/vis_helper.c
+++ b/target-sparc/vis_helper.c
@@ -28,8 +28,7 @@
#define GET_FIELD_SP(X, FROM, TO) \
GET_FIELD(X, 63 - (TO), 63 - (FROM))
-target_ulong helper_array8(CPUState *env, target_ulong pixel_addr,
- target_ulong cubesize)
+target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize)
{
return (GET_FIELD_SP(pixel_addr, 60, 63) << (17 + 2 * cubesize)) |
(GET_FIELD_SP(pixel_addr, 39, 39 + cubesize - 1) << (17 + cubesize)) |
@@ -97,7 +96,7 @@ typedef union {
float32 f;
} VIS32;
-uint64_t helper_fpmerge(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fpmerge(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
@@ -117,7 +116,7 @@ uint64_t helper_fpmerge(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmul8x16(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8x16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -141,7 +140,7 @@ uint64_t helper_fmul8x16(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmul8x16al(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8x16al(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -165,7 +164,7 @@ uint64_t helper_fmul8x16al(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmul8x16au(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8x16au(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -189,7 +188,7 @@ uint64_t helper_fmul8x16au(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmul8sux16(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8sux16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -213,7 +212,7 @@ uint64_t helper_fmul8sux16(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmul8ulx16(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmul8ulx16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -237,7 +236,7 @@ uint64_t helper_fmul8ulx16(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmuld8sux16(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmuld8sux16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -260,7 +259,7 @@ uint64_t helper_fmuld8sux16(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fmuld8ulx16(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fmuld8ulx16(uint64_t src1, uint64_t src2)
{
VIS64 s, d;
uint32_t tmp;
@@ -283,7 +282,7 @@ uint64_t helper_fmuld8ulx16(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll;
}
-uint64_t helper_fexpand(CPUState *env, uint64_t src1, uint64_t src2)
+uint64_t helper_fexpand(uint64_t src1, uint64_t src2)
{
VIS32 s;
VIS64 d;
@@ -299,7 +298,7 @@ uint64_t helper_fexpand(CPUState *env, uint64_t src1,
uint64_t src2)
}
#define VIS_HELPER(name, F) \
- uint64_t name##16(CPUState *env, uint64_t src1, uint64_t src2) \
+ uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
@@ -314,8 +313,7 @@ uint64_t helper_fexpand(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll; \
} \
\
- uint32_t name##16s(CPUState *env, uint32_t src1, \
- uint32_t src2) \
+ uint32_t name##16s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
@@ -328,7 +326,7 @@ uint64_t helper_fexpand(CPUState *env, uint64_t src1,
uint64_t src2)
return d.l; \
} \
\
- uint64_t name##32(CPUState *env, uint64_t src1, uint64_t src2) \
+ uint64_t name##32(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
@@ -341,8 +339,7 @@ uint64_t helper_fexpand(CPUState *env, uint64_t src1,
uint64_t src2)
return d.ll; \
} \
\
- uint32_t name##32s(CPUState *env, uint32_t src1, \
- uint32_t src2) \
+ uint32_t name##32s(uint32_t src1, uint32_t src2) \
{ \
VIS32 s, d; \
\
@@ -360,7 +357,7 @@ VIS_HELPER(helper_fpadd, FADD)
VIS_HELPER(helper_fpsub, FSUB)
#define VIS_CMPHELPER(name, F) \
- uint64_t name##16(CPUState *env, uint64_t src1, uint64_t src2) \
+ uint64_t name##16(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
@@ -376,7 +373,7 @@ VIS_HELPER(helper_fpsub, FSUB)
return d.ll; \
} \
\
- uint64_t name##32(CPUState *env, uint64_t src1, uint64_t src2) \
+ uint64_t name##32(uint64_t src1, uint64_t src2) \
{ \
VIS64 s, d; \
\
--
1.7.6.4
- [Qemu-devel] [PATCH v2 00/16] Sparc FPU/VIS improvements, Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 02/16] target-sparc: Mark fprs dirty in store accessor., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 01/16] target-sparc: Add accessors for single-precision fpr access., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 03/16] target-sparc: Add accessors for double-precision fpr access., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 07/16] target-sparc: Extract float128 move to a function., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 05/16] target-sparc: Make FPU/VIS helpers const when possible.,
Richard Henderson <=
- [Qemu-devel] [PATCH 04/16] target-sparc: Pass float64 parameters instead of dt0/1 temporaries., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 06/16] target-sparc: Extract common code for floating-point operations., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 10/16] target-sparc: Do exceptions management fully inside the helpers., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 08/16] target-sparc: Undo cpu_fpr rename., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 11/16] target-sparc: Implement PDIST., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 13/16] target-sparc: Implement EDGE* instructions., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 12/16] target-sparc: Implement fpack{16, 32, fix}., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 14/16] target-sparc: Implement ALIGNADDR* inline., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 09/16] target-sparc: Change fpr representation to doubles., Richard Henderson, 2011/10/26
- [Qemu-devel] [PATCH 15/16] target-sparc: Implement BMASK/BSHUFFLE., Richard Henderson, 2011/10/26