Re: [Qemu-devel] Multi heterogenous CPU archs for SoC sim?

[Peter Maydell]

On 21 October 2011 23:05, Andreas Färber <address@hidden> wrote:
> Am 21.10.2011 08:58, schrieb Peter Maydell:
>> (For several
>> of the ARM boards we currently just ignore the fact that the real
>> h/w has a Cortex-M3 doing power management type stuff.)
>
> Mind to share which boards? I'm only aware of the NXP LPC43xx asymmetric
> SoC (Cortex-M4 + Cortex-M0), which still is in development stage.

I had in mind the Versatile Express -- the main core is an A9x4
but there is also an M3 on the board. (There are some other
interestng ARM based heterogeneous architectures coming
up too, like the nVidia Tegra3 with 4xA9+1xA9, and the ARM
big.LITTLE systems with 4xA7+4xA15.)

> The
> datasheet doesn't really enlighten me how such a combo is supposed to
> work in shared memory: Do all ARM cores share a reset vector (or what
> you call it on arm) so that one has to branch based on CPUID to do
> different tasks on different cores?

In general a multicore bootup will use the core ID to figure out
what it is at reset. I don't know what a multicluster system
would do, but probably the same thing. The other approach I've
seen is that you can give the two CPUs different memory maps
so they share most things but have different memory layouts
where the vector table/startup code is. Or you could have
the power controller hold the secondary core in reset until
the primary core has booted, and have your boot code work
differently for first and second execution, I guess.

(The reset architecture on M profile and AR profiles is different,
but I don't think the differences are important for these purposes.)

-- PMM