Re: [Qemu-devel] [PATCH] target-xtensa: update qemu-doc.texi

[Blue Swirl]

Thanks, applied.

On Mon, Oct 10, 2011 at 2:25 AM, Max Filippov <address@hidden> wrote:
> Signed-off-by: Max Filippov <address@hidden>
> ---
>  qemu-doc.texi  |   55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  qemu-tech.texi |   40 +++++++++++++++++++++++++++++++++-------
>  2 files changed, 88 insertions(+), 7 deletions(-)
>
> diff --git a/qemu-doc.texi b/qemu-doc.texi
> index 31199f6..ad19b73 100644
> --- a/qemu-doc.texi
> +++ b/qemu-doc.texi
> @@ -110,6 +110,7 @@ For system emulation, the following hardware targets are 
> supported:
> address@hidden Syborg SVP base model (ARM Cortex-A8).
> address@hidden AXIS-Devboard88 (CRISv32 ETRAX-FS).
> address@hidden Petalogix Spartan 3aDSP1800 MMU ref design (MicroBlaze).
> address@hidden Avnet LX60/LX110/LX200 boards (Xtensa)
> address@hidden itemize
>
> address@hidden supported user mode targets
> @@ -1446,6 +1447,7 @@ differences are mentioned in the following sections.
>  * Cris System emulator::
>  * Microblaze System emulator::
>  * SH4 System emulator::
> +* Xtensa System emulator::
> address@hidden menu
>
> address@hidden PowerPC System emulator
> @@ -2124,6 +2126,59 @@ TODO
>
>  TODO
>
> address@hidden Xtensa System emulator
> address@hidden Xtensa System emulator
> address@hidden system emulation (Xtensa)
> +
> +Two executables cover simulation of both Xtensa endian options,
> address@hidden and @file{qemu-system-xtensaeb}.
> +Two different machine types are emulated:
> +
> address@hidden @minus
> address@hidden
> +Xtensa emulator pseudo board "sim"
> address@hidden
> +Avnet LX60/LX110/LX200 board
> address@hidden itemize
> +
> +The sim pseudo board emulation provides an environment similiar
> +to one provided by the proprietary Tensilica ISS.
> +It supports:
> +
> address@hidden @minus
> address@hidden
> +A range of Xtensa CPUs, default is the DC232B
> address@hidden
> +Console and filesystem access via semihosting calls
> address@hidden itemize
> +
> +The Avnet LX60/LX110/LX200 emulation supports:
> +
> address@hidden @minus
> address@hidden
> +A range of Xtensa CPUs, default is the DC232B
> address@hidden
> +16550 UART
> address@hidden
> +OpenCores 10/100 Mbps Ethernet MAC
> address@hidden itemize
> +
> address@hidden man begin OPTIONS
> +
> +The following options are specific to the Xtensa emulation:
> +
> address@hidden @option
> +
> address@hidden -semihosting
> +Enable semihosting syscall emulation.
> +
> +Xtensa semihosting provides basic file IO calls, such as 
> open/read/write/seek/select.
> +Tensilica baremetal libc for ISS and linux platform "sim" use this interface.
> +
> +Note that this allows guest direct access to the host filesystem,
> +so should only be used with trusted guest OS.
> +
> address@hidden table
> address@hidden QEMU User space emulator
> address@hidden QEMU User space emulator
>
> diff --git a/qemu-tech.texi b/qemu-tech.texi
> index 138e3ce..c6bdc28 100644
> --- a/qemu-tech.texi
> +++ b/qemu-tech.texi
> @@ -42,13 +42,14 @@
> address@hidden Introduction
>
> address@hidden
> -* intro_features::        Features
> -* intro_x86_emulation::   x86 and x86-64 emulation
> -* intro_arm_emulation::   ARM emulation
> -* intro_mips_emulation::  MIPS emulation
> -* intro_ppc_emulation::   PowerPC emulation
> -* intro_sparc_emulation:: Sparc32 and Sparc64 emulation
> -* intro_other_emulation:: Other CPU emulation
> +* intro_features::         Features
> +* intro_x86_emulation::    x86 and x86-64 emulation
> +* intro_arm_emulation::    ARM emulation
> +* intro_mips_emulation::   MIPS emulation
> +* intro_ppc_emulation::    PowerPC emulation
> +* intro_sparc_emulation::  Sparc32 and Sparc64 emulation
> +* intro_xtensa_emulation:: MIPS emulation
> +* intro_other_emulation::  Other CPU emulation
> address@hidden menu
>
> address@hidden intro_features
> @@ -259,6 +260,31 @@ Current QEMU limitations:
>
> address@hidden itemize
>
> address@hidden intro_xtensa_emulation
> address@hidden Xtensa emulation
> +
> address@hidden
> +
> address@hidden Core Xtensa ISA emulation, including most options: code 
> density,
> +loop, extended L32R, 16- and 32-bit multiplication, 32-bit division,
> +MAC16, miscellaneous operations, boolean, multiprocessor synchronization,
> +conditional store, exceptions, relocatable vectors, unaligned exception,
> +interrupts (including high priority and timer), hardware alignment,
> +region protection, region translation, MMU, windowed registers, thread
> +pointer, processor ID.
> +
> address@hidden Not implemented options: FP coprocessor, coprocessor context,
> +data/instruction cache (including cache prefetch and locking), XLMI,
> +processor interface, debug. Also options not covered by the core ISA
> +(e.g. FLIX, wide branches) are not implemented.
> +
> address@hidden Can run most Xtensa Linux binaries.
> +
> address@hidden New core configuration that requires no additional instructions
> +may be created from overlay with minimal amount of hand-written code.
> +
> address@hidden itemize
> +
> address@hidden intro_other_emulation
> address@hidden Other CPU emulation
>
> --
> 1.7.6.4
>
>
>