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[Qemu-devel] [PATCH v5 05/33] target-xtensa: implement RT0 group
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH v5 05/33] target-xtensa: implement RT0 group |
Date: |
Tue, 6 Sep 2011 03:55:29 +0400 |
NEG and ABS are the only members of RT0 group.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/translate.c | 19 +++++++++++++++++++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 4dfca2b..92547d2 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -255,6 +255,25 @@ static void disas_xtensa_insn(DisasContext *dc)
break;
case 6: /*RT0*/
+ switch (RRR_S) {
+ case 0: /*NEG*/
+ tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
+ break;
+
+ case 1: /*ABS*/
+ {
+ int label = gen_new_label();
+ tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
+ tcg_gen_brcondi_i32(
+ TCG_COND_GE, cpu_R[RRR_R], 0, label);
+ tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
+ gen_set_label(label);
+ }
+ break;
+
+ default: /*reserved*/
+ break;
+ }
break;
case 7: /*reserved*/
--
1.7.6
- [Qemu-devel] [PATCH v5 00/32] target-xtensa: new target architecture, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 04/33] target-xtensa: implement narrow instructions, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 02/33] target-xtensa: add target to the configure script, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 07/33] target-xtensa: implement conditional jumps, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 01/33] target-xtensa: add target stubs, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 03/33] target-xtensa: implement disas_xtensa_insn, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 08/33] target-xtensa: implement JX/RET0/CALLX, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 06/33] target-xtensa: add sample board, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 14/33] target-xtensa: implement SYNC group, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 11/33] target-xtensa: implement shifts (ST1 and RST1 groups), Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 05/33] target-xtensa: implement RT0 group,
Max Filippov <=
- [Qemu-devel] [PATCH v5 10/33] target-xtensa: implement RST3 group, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 12/33] target-xtensa: implement LSAI group, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 13/33] target-xtensa: mark reserved and TBD opcodes, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 18/33] target-xtensa: implement RST2 group (32 bit mul/div/rem), Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 30/33] target-xtensa: implement boolean option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 23/33] target-xtensa: implement SIMCALL, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 22/33] target-xtensa: implement unaligned exception option, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 26/33] target-xtensa: implement CPENABLE and PRID SRs, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 16/33] target-xtensa: add PS register and access control, Max Filippov, 2011/09/05
- [Qemu-devel] [PATCH v5 20/33] target-xtensa: implement loop option, Max Filippov, 2011/09/05