Re: [Qemu-devel] [PATCH 2/2] g364fb: convert to qdev

[Blue Swirl]

Thanks, applied.

2011/8/26 Hervé Poussineau <address@hidden>:
> Extract G364 ROM contents from device emulation to machine emulation,
> so device emulation can be reused in other machines (Commodore Amiga)
>
> Signed-off-by: Hervé Poussineau <address@hidden>
> ---
>  hw/g364fb.c    |  340 
> +++++++++++++++++++++++++-------------------------------
>  hw/mips.h      |    5 -
>  hw/mips_jazz.c |   15 +++-
>  3 files changed, 164 insertions(+), 196 deletions(-)
>
> diff --git a/hw/g364fb.c b/hw/g364fb.c
> index fa074f4..5e7bcfa 100644
> --- a/hw/g364fb.c
> +++ b/hw/g364fb.c
> @@ -1,7 +1,7 @@
>  /*
>  * QEMU G364 framebuffer Emulator.
>  *
> - * Copyright (c) 2007-2009 Herve Poussineau
> + * Copyright (c) 2007-2011 Herve Poussineau
>  *
>  * This program is free software; you can redistribute it and/or
>  * modify it under the terms of the GNU General Public License as
> @@ -18,17 +18,18 @@
>  */
>
>  #include "hw.h"
> -#include "mips.h"
>  #include "console.h"
>  #include "pixel_ops.h"
>  #include "trace.h"
> +#include "sysbus.h"
>
>  typedef struct G364State {
>     /* hardware */
>     uint8_t *vram;
> -    ram_addr_t vram_offset;
> -    int vram_size;
> +    uint32_t vram_size;
>     qemu_irq irq;
> +    MemoryRegion mem_vram;
> +    MemoryRegion mem_ctrl;
>     /* registers */
>     uint8_t color_palette[256][3];
>     uint8_t cursor_palette[3][3];
> @@ -43,31 +44,32 @@ typedef struct G364State {
>     int blanked;
>  } G364State;
>
> -#define REG_ID       0x000000
> -#define REG_BOOT     0x080000
> -#define REG_DISPLAY  0x080118
> -#define REG_VDISPLAY 0x080150
> -#define REG_CTLA     0x080300
> -#define REG_TOP      0x080400
> -#define REG_CURS_PAL 0x080508
> -#define REG_CURS_POS 0x080638
> -#define REG_CLR_PAL  0x080800
> -#define REG_CURS_PAT 0x081000
> -#define REG_RESET    0x180000
> +#define REG_BOOT     0x000000
> +#define REG_DISPLAY  0x000118
> +#define REG_VDISPLAY 0x000150
> +#define REG_CTLA     0x000300
> +#define REG_TOP      0x000400
> +#define REG_CURS_PAL 0x000508
> +#define REG_CURS_POS 0x000638
> +#define REG_CLR_PAL  0x000800
> +#define REG_CURS_PAT 0x001000
> +#define REG_RESET    0x100000
>
>  #define CTLA_FORCE_BLANK 0x00000400
>  #define CTLA_NO_CURSOR   0x00800000
>
> -static inline int check_dirty(ram_addr_t page)
> +static inline int check_dirty(G364State *s, ram_addr_t page)
>  {
> -    return cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
> +    return memory_region_get_dirty(&s->mem_vram, page, DIRTY_MEMORY_VGA);
>  }
>
>  static inline void reset_dirty(G364State *s,
>                                ram_addr_t page_min, ram_addr_t page_max)
>  {
> -    cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE - 
> 1,
> -                                    VGA_DIRTY_FLAG);
> +    memory_region_reset_dirty(&s->mem_vram,
> +                              page_min,
> +                              page_max + TARGET_PAGE_SIZE - page_min - 1,
> +                              DIRTY_MEMORY_VGA);
>  }
>
>  static void g364fb_draw_graphic8(G364State *s)
> @@ -105,7 +107,7 @@ static void g364fb_draw_graphic8(G364State *s)
>             return;
>     }
>
> -    page = s->vram_offset;
> +    page = 0;
>     page_min = (ram_addr_t)-1;
>     page_max = 0;
>
> @@ -126,7 +128,7 @@ static void g364fb_draw_graphic8(G364State *s)
>     /* XXX: out of range in vram? */
>     data_display = dd = ds_get_data(s->ds);
>     while (y < s->height) {
> -        if (check_dirty(page)) {
> +        if (check_dirty(s, page)) {
>             if (y < ymin)
>                 ymin = ymax = y;
>             if (page_min == (ram_addr_t)-1)
> @@ -266,13 +268,12 @@ static inline void g364fb_invalidate_display(void 
> *opaque)
>
>     s->blanked = 0;
>     for (i = 0; i < s->vram_size; i += TARGET_PAGE_SIZE) {
> -        cpu_physical_memory_set_dirty(s->vram_offset + i);
> +        memory_region_set_dirty(&s->mem_vram, i);
>     }
>  }
>
> -static void g364fb_reset(void *opaque)
> +static void g364fb_reset(G364State *s)
>  {
> -    G364State *s = opaque;
>     qemu_irq_lower(s->irq);
>
>     memset(s->color_palette, 0, sizeof(s->color_palette));
> @@ -283,7 +284,7 @@ static void g364fb_reset(void *opaque)
>     s->top_of_screen = 0;
>     s->width = s->height = 0;
>     memset(s->vram, 0, s->vram_size);
> -    g364fb_invalidate_display(opaque);
> +    g364fb_invalidate_display(s);
>  }
>
>  static void g364fb_screen_dump(void *opaque, const char *filename)
> @@ -327,7 +328,9 @@ static void g364fb_screen_dump(void *opaque, const char 
> *filename)
>  }
>
>  /* called for accesses to io ports */
> -static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr)
> +static uint64_t g364fb_ctrl_read(void *opaque,
> +                                 target_phys_addr_t addr,
> +                                 unsigned int size)
>  {
>     G364State *s = opaque;
>     uint32_t val;
> @@ -344,9 +347,6 @@ static uint32_t g364fb_ctrl_readl(void *opaque, 
> target_phys_addr_t addr)
>         val |= ((uint32_t)s->cursor_palette[idx][2] << 0);
>     } else {
>         switch (addr) {
> -            case REG_ID:
> -                val = 0x10; /* Mips G364 */
> -                break;
>             case REG_DISPLAY:
>                 val = s->width / 4;
>                 break;
> @@ -371,21 +371,6 @@ static uint32_t g364fb_ctrl_readl(void *opaque, 
> target_phys_addr_t addr)
>     return val;
>  }
>
> -static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr)
> -{
> -    uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
> -    if (addr & 0x2)
> -        return v >> 16;
> -    else
> -        return v & 0xffff;
> -}
> -
> -static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr)
> -{
> -    uint32_t v = g364fb_ctrl_readl(opaque, addr & ~0x3);
> -    return (v >> (8 * (addr & 0x3))) & 0xff;
> -}
> -
>  static void g364fb_update_depth(G364State *s)
>  {
>     static const int depths[8] = { 1, 2, 4, 8, 15, 16, 0 };
> @@ -403,11 +388,14 @@ static void g364_invalidate_cursor_position(G364State 
> *s)
>     end = (ymax + 1) * ds_get_linesize(s->ds);
>
>     for (i = start; i < end; i += TARGET_PAGE_SIZE) {
> -        cpu_physical_memory_set_dirty(s->vram_offset + i);
> +        memory_region_set_dirty(&s->mem_vram, i);
>     }
>  }
>
> -static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, 
> uint32_t val)
> +static void g364fb_ctrl_write(void *opaque,
> +                              target_phys_addr_t addr,
> +                              uint64_t val,
> +                              unsigned int size)
>  {
>     G364State *s = opaque;
>
> @@ -434,121 +422,65 @@ static void g364fb_ctrl_writel(void *opaque, 
> target_phys_addr_t addr, uint32_t v
>         g364fb_invalidate_display(s);
>     } else {
>         switch (addr) {
> -            case REG_ID: /* Card identifier; read-only */
> -            case REG_BOOT: /* Boot timing */
> -            case 0x80108: /* Line timing: half sync */
> -            case 0x80110: /* Line timing: back porch */
> -            case 0x80120: /* Line timing: short display */
> -            case 0x80128: /* Frame timing: broad pulse */
> -            case 0x80130: /* Frame timing: v sync */
> -            case 0x80138: /* Frame timing: v preequalise */
> -            case 0x80140: /* Frame timing: v postequalise */
> -            case 0x80148: /* Frame timing: v blank */
> -            case 0x80158: /* Line timing: line time */
> -            case 0x80160: /* Frame store: line start */
> -            case 0x80168: /* vram cycle: mem init */
> -            case 0x80170: /* vram cycle: transfer delay */
> -            case 0x80200: /* vram cycle: mask register */
> -                /* ignore */
> -                break;
> -            case REG_TOP:
> -                s->top_of_screen = val;
> -                g364fb_invalidate_display(s);
> -                break;
> -            case REG_DISPLAY:
> -                s->width = val * 4;
> -                break;
> -            case REG_VDISPLAY:
> -                s->height = val / 2;
> -                break;
> -            case REG_CTLA:
> -                s->ctla = val;
> -                g364fb_update_depth(s);
> -                g364fb_invalidate_display(s);
> -                break;
> -            case REG_CURS_POS:
> -                g364_invalidate_cursor_position(s);
> -                s->cursor_position = val;
> -                g364_invalidate_cursor_position(s);
> -                break;
> -            case REG_RESET:
> -                g364fb_reset(s);
> -                break;
> -            default:
> -                error_report("g364: invalid write of 0x%" PRIx64
> -                             " at [" TARGET_FMT_plx "]", val, addr);
> -                break;
> +        case REG_BOOT: /* Boot timing */
> +        case 0x00108: /* Line timing: half sync */
> +        case 0x00110: /* Line timing: back porch */
> +        case 0x00120: /* Line timing: short display */
> +        case 0x00128: /* Frame timing: broad pulse */
> +        case 0x00130: /* Frame timing: v sync */
> +        case 0x00138: /* Frame timing: v preequalise */
> +        case 0x00140: /* Frame timing: v postequalise */
> +        case 0x00148: /* Frame timing: v blank */
> +        case 0x00158: /* Line timing: line time */
> +        case 0x00160: /* Frame store: line start */
> +        case 0x00168: /* vram cycle: mem init */
> +        case 0x00170: /* vram cycle: transfer delay */
> +        case 0x00200: /* vram cycle: mask register */
> +            /* ignore */
> +            break;
> +        case REG_TOP:
> +            s->top_of_screen = val;
> +            g364fb_invalidate_display(s);
> +            break;
> +        case REG_DISPLAY:
> +            s->width = val * 4;
> +            break;
> +        case REG_VDISPLAY:
> +            s->height = val / 2;
> +            break;
> +        case REG_CTLA:
> +            s->ctla = val;
> +            g364fb_update_depth(s);
> +            g364fb_invalidate_display(s);
> +            break;
> +        case REG_CURS_POS:
> +            g364_invalidate_cursor_position(s);
> +            s->cursor_position = val;
> +            g364_invalidate_cursor_position(s);
> +            break;
> +        case REG_RESET:
> +            g364fb_reset(s);
> +            break;
> +        default:
> +            error_report("g364: invalid write of 0x%" PRIx64
> +                         " at [" TARGET_FMT_plx "]", val, addr);
> +            break;
>         }
>     }
>     qemu_irq_lower(s->irq);
>  }
>
> -static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, 
> uint32_t val)
> -{
> -    uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
> -
> -    if (addr & 0x2)
> -        val = (val << 16) | (old_val & 0x0000ffff);
> -    else
> -        val = val | (old_val & 0xffff0000);
> -    g364fb_ctrl_writel(opaque, addr & ~0x3, val);
> -}
> -
> -static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, 
> uint32_t val)
> -{
> -    uint32_t old_val = g364fb_ctrl_readl(opaque, addr & ~0x3);
> -
> -    switch (addr & 3) {
> -    case 0:
> -        val = val | (old_val & 0xffffff00);
> -        break;
> -    case 1:
> -        val = (val << 8) | (old_val & 0xffff00ff);
> -        break;
> -    case 2:
> -        val = (val << 16) | (old_val & 0xff00ffff);
> -        break;
> -    case 3:
> -        val = (val << 24) | (old_val & 0x00ffffff);
> -        break;
> -    }
> -    g364fb_ctrl_writel(opaque, addr & ~0x3, val);
> -}
> -
> -static CPUReadMemoryFunc * const g364fb_ctrl_read[3] = {
> -    g364fb_ctrl_readb,
> -    g364fb_ctrl_readw,
> -    g364fb_ctrl_readl,
> -};
> -
> -static CPUWriteMemoryFunc * const g364fb_ctrl_write[3] = {
> -    g364fb_ctrl_writeb,
> -    g364fb_ctrl_writew,
> -    g364fb_ctrl_writel,
> +static const MemoryRegionOps g364fb_ctrl_ops = {
> +    .read = g364fb_ctrl_read,
> +    .write = g364fb_ctrl_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .impl.min_access_size = 4,
> +    .impl.max_access_size = 4,
>  };
>
> -static int g364fb_load(QEMUFile *f, void *opaque, int version_id)
> +static int g364fb_post_load(void *opaque, int version_id)
>  {
>     G364State *s = opaque;
> -    unsigned int i, vram_size;
> -
> -    if (version_id != 1)
> -        return -EINVAL;
> -
> -    vram_size = qemu_get_be32(f);
> -    if (vram_size < s->vram_size)
> -        return -EINVAL;
> -    qemu_get_buffer(f, s->vram, s->vram_size);
> -    for (i = 0; i < 256; i++)
> -        qemu_get_buffer(f, s->color_palette[i], 3);
> -    for (i = 0; i < 3; i++)
> -        qemu_get_buffer(f, s->cursor_palette[i], 3);
> -    qemu_get_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
> -    s->cursor_position = qemu_get_be32(f);
> -    s->ctla = qemu_get_be32(f);
> -    s->top_of_screen = qemu_get_be32(f);
> -    s->width = qemu_get_be32(f);
> -    s->height = qemu_get_be32(f);
>
>     /* force refresh */
>     g364fb_update_depth(s);
> @@ -557,52 +489,80 @@ static int g364fb_load(QEMUFile *f, void *opaque, int 
> version_id)
>     return 0;
>  }
>
> -static void g364fb_save(QEMUFile *f, void *opaque)
> -{
> -    G364State *s = opaque;
> -    int i;
> -
> -    qemu_put_be32(f, s->vram_size);
> -    qemu_put_buffer(f, s->vram, s->vram_size);
> -    for (i = 0; i < 256; i++)
> -        qemu_put_buffer(f, s->color_palette[i], 3);
> -    for (i = 0; i < 3; i++)
> -        qemu_put_buffer(f, s->cursor_palette[i], 3);
> -    qemu_put_buffer(f, (uint8_t *)s->cursor, sizeof(s->cursor));
> -    qemu_put_be32(f, s->cursor_position);
> -    qemu_put_be32(f, s->ctla);
> -    qemu_put_be32(f, s->top_of_screen);
> -    qemu_put_be32(f, s->width);
> -    qemu_put_be32(f, s->height);
> -}
> +static const VMStateDescription vmstate_g364fb = {
> +    .name = "g364fb",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .minimum_version_id_old = 1,
> +    .post_load = g364fb_post_load,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_VBUFFER_UINT32(vram, G364State, 1, NULL, 0, vram_size),
> +        VMSTATE_BUFFER_UNSAFE(color_palette, G364State, 0, 256 * 3),
> +        VMSTATE_BUFFER_UNSAFE(cursor_palette, G364State, 0, 9),
> +        VMSTATE_UINT16_ARRAY(cursor, G364State, 512),
> +        VMSTATE_UINT32(cursor_position, G364State),
> +        VMSTATE_UINT32(ctla, G364State),
> +        VMSTATE_UINT32(top_of_screen, G364State),
> +        VMSTATE_UINT32(width, G364State),
> +        VMSTATE_UINT32(height, G364State),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
>
> -int g364fb_mm_init(target_phys_addr_t vram_base,
> -                   target_phys_addr_t ctrl_base, int it_shift,
> -                   qemu_irq irq)
> +static void g364fb_init(DeviceState *dev, G364State *s)
>  {
> -    G364State *s;
> -    int io_ctrl;
> -
> -    s = g_malloc0(sizeof(G364State));
> -
> -    s->vram_size = 8 * 1024 * 1024;
> -    s->vram_offset = qemu_ram_alloc(NULL, "g364fb.vram", s->vram_size);
> -    s->vram = qemu_get_ram_ptr(s->vram_offset);
> -    s->irq = irq;
> -
> -    qemu_register_reset(g364fb_reset, s);
> -    register_savevm(NULL, "g364fb", 0, 1, g364fb_save, g364fb_load, s);
> -    g364fb_reset(s);
> +    s->vram = g_malloc0(s->vram_size);
>
>     s->ds = graphic_console_init(g364fb_update_display,
>                                  g364fb_invalidate_display,
>                                  g364fb_screen_dump, NULL, s);
>
> -    cpu_register_physical_memory(vram_base, s->vram_size, s->vram_offset);
> +    memory_region_init_io(&s->mem_ctrl, &g364fb_ctrl_ops, s, "ctrl", 
> 0x180000);
> +    memory_region_init_ram_ptr(&s->mem_vram, dev, "vram",
> +                               s->vram_size, s->vram);
> +    memory_region_set_coalescing(&s->mem_vram);
> +}
> +
> +typedef struct {
> +    SysBusDevice busdev;
> +    G364State g364;
> +} G364SysBusState;
>
> -    io_ctrl = cpu_register_io_memory(g364fb_ctrl_read, g364fb_ctrl_write, s,
> -                                     DEVICE_NATIVE_ENDIAN);
> -    cpu_register_physical_memory(ctrl_base, 0x200000, io_ctrl);
> +static int g364fb_sysbus_init(SysBusDevice *dev)
> +{
> +    G364State *s = &FROM_SYSBUS(G364SysBusState, dev)->g364;
> +
> +    g364fb_init(&dev->qdev, s);
> +    sysbus_init_irq(dev, &s->irq);
> +    sysbus_init_mmio_region(dev, &s->mem_ctrl);
> +    sysbus_init_mmio_region(dev, &s->mem_vram);
>
>     return 0;
>  }
> +
> +static void g364fb_sysbus_reset(DeviceState *d)
> +{
> +    G364SysBusState *s = DO_UPCAST(G364SysBusState, busdev.qdev, d);
> +    g364fb_reset(&s->g364);
> +}
> +
> +static SysBusDeviceInfo g364fb_sysbus_info = {
> +    .init = g364fb_sysbus_init,
> +    .qdev.name = "sysbus-g364",
> +    .qdev.desc = "G364 framebuffer",
> +    .qdev.size = sizeof(G364SysBusState),
> +    .qdev.vmsd = &vmstate_g364fb,
> +    .qdev.reset = g364fb_sysbus_reset,
> +    .qdev.props = (Property[]) {
> +        DEFINE_PROP_HEX32("vram_size", G364SysBusState, g364.vram_size,
> +                          8 * 1024 * 1024),
> +        DEFINE_PROP_END_OF_LIST(),
> +    }
> +};
> +
> +static void g364fb_register(void)
> +{
> +    sysbus_register_withprop(&g364fb_sysbus_info);
> +}
> +
> +device_init(g364fb_register);
> diff --git a/hw/mips.h b/hw/mips.h
> index cae5f4c..8ce41fc 100644
> --- a/hw/mips.h
> +++ b/hw/mips.h
> @@ -8,11 +8,6 @@ PCIBus *gt64120_register(qemu_irq *pic);
>  /* bonito.c */
>  PCIBus *bonito_init(qemu_irq *pic);
>
> -/* g364fb.c */
> -int g364fb_mm_init(target_phys_addr_t vram_base,
> -                   target_phys_addr_t ctrl_base, int it_shift,
> -                   qemu_irq irq);
> -
>  /* mipsnet.c */
>  void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
>
> diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
> index 84ce061..f3c9f93 100644
> --- a/hw/mips_jazz.c
> +++ b/hw/mips_jazz.c
> @@ -195,7 +195,20 @@ void mips_jazz_init (ram_addr_t ram_size,
>     /* Video card */
>     switch (jazz_model) {
>     case JAZZ_MAGNUM:
> -        g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
> +        dev = qdev_create(NULL, "sysbus-g364");
> +        qdev_init_nofail(dev);
> +        sysbus = sysbus_from_qdev(dev);
> +        sysbus_mmio_map(sysbus, 0, 0x60080000);
> +        sysbus_mmio_map(sysbus, 1, 0x40000000);
> +        sysbus_connect_irq(sysbus, 0, rc4030[3]);
> +        {
> +            /* Simple ROM, so user doesn't have to provide one */
> +            ram_addr_t rom_offset = qemu_ram_alloc(NULL, "g364fb.rom", 
> 0x80000);
> +            uint8_t *rom = qemu_get_ram_ptr(rom_offset);
> +            cpu_register_physical_memory(0x60000000, 0x80000,
> +                                         rom_offset | IO_MEM_ROM);
> +            rom[0] = 0x10; /* Mips G364 */
> +        }
>         break;
>     case JAZZ_PICA61:
>         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
> --
> 1.7.5.4
>
>
>