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[Qemu-devel] [PATCH 025/111] m68k: add cas
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 025/111] m68k: add cas |
Date: |
Wed, 17 Aug 2011 15:46:30 -0500 |
From: Andreas Schwab <address@hidden>
Laurent Vivier <address@hidden> writes:
> + cmp = DREG(ext, 0);
> + update = DREG(ext, 6);
> + tmp = gen_load(s, opsize, addr, 0);
> + dest = tcg_temp_local_new();
> + tcg_gen_mov_i32(dest, tmp);
> +
> + res = tcg_temp_new();
> + tcg_gen_sub_i32(res, dest, cmp);
> + gen_logic_cc(s, res);
> +
> + l1 = gen_new_label();
> + l2 = gen_new_label();
> +
> + gen_jmpcc(s, 6 /* !Z */, l1);
> + gen_store(s, opsize, addr, update);
This has a bug: addr is used around a jump.
Andreas.
---
target-m68k/translate.c | 10 +++++++---
1 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index c186fe1..218210c 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -1378,6 +1378,7 @@ DISAS_INSN(cas)
TCGv tmp;
TCGv cmp;
TCGv update;
+ TCGv taddr;
TCGv addr;
TCGv res;
uint16_t ext;
@@ -1404,17 +1405,19 @@ DISAS_INSN(cas)
ext = lduw_code(s->pc);
s->pc += 2;
- addr = gen_lea(s, insn, opsize);
- if (IS_NULL_QREG(addr)) {
+ taddr = gen_lea(s, insn, opsize);
+ if (IS_NULL_QREG(taddr)) {
gen_addr_fault(s);
return;
}
cmp = DREG(ext, 0);
update = DREG(ext, 6);
- tmp = gen_load(s, opsize, addr, 0);
+ tmp = gen_load(s, opsize, taddr, 0);
dest = tcg_temp_local_new();
tcg_gen_mov_i32(dest, tmp);
+ addr = tcg_temp_local_new ();
+ tcg_gen_mov_i32(addr, taddr);
res = tcg_temp_new();
tcg_gen_sub_i32(res, dest, cmp);
@@ -1430,6 +1433,7 @@ DISAS_INSN(cas)
tcg_gen_mov_i32(cmp, dest);
gen_set_label(l2);
tcg_temp_free(dest);
+ tcg_temp_free(addr);
}
DISAS_INSN(byterev)
--
1.7.2.3
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, (continued)
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Laurent Vivier, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
- Re: [Qemu-devel] [RFC][PATCH 000/111] QEMU m68k core additions, Rob Landley, 2011/08/20
[Qemu-devel] [PATCH 086/111] m68k: correct bfins instruction, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 025/111] m68k: add cas,
Bryce Lanham <=
[Qemu-devel] [PATCH 067/111] m68k: add fscale, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 033/111] m68k: Add fmovecr, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 058/111] m68k: correctly compute divul, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 069/111] m68k: add fetox and flogn, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 048/111] m68k: correct shift side effect for roxrl and roxll, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 065/111] m68k: correct compute gen_bitfield_cc(), Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 049/111] m68k: asl/asr, clear C flag if shift count is 0, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 044/111] m68k: improve addx instructions Add (byte, word) opsize Add memory access, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 046/111] m68k: improve asl/asr evaluate correclty the missing V flag, Bryce Lanham, 2011/08/17
[Qemu-devel] [PATCH 023/111] m68k: add variable offset/width to bitfield_reg/bitfield_mem, Bryce Lanham, 2011/08/17