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[Qemu-devel] [PATCH 12/15] onenand: Pass BlockDriverState to init functi
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/15] onenand: Pass BlockDriverState to init function |
Date: |
Fri, 29 Jul 2011 16:35:25 +0100 |
Pass the BlockDriverState to the onenand init function so it doesn't
need to look up the drive itself.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/flash.h | 3 ++-
hw/nseries.c | 10 ++++++----
hw/onenand.c | 14 ++++++++------
3 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/hw/flash.h b/hw/flash.h
index 43260ce..1aae43d 100644
--- a/hw/flash.h
+++ b/hw/flash.h
@@ -38,7 +38,8 @@ uint32_t nand_getbuswidth(DeviceState *dev);
/* onenand.c */
void onenand_base_update(void *opaque, target_phys_addr_t new);
void onenand_base_unmap(void *opaque);
-void *onenand_init(uint32_t id, int regshift, qemu_irq irq);
+void *onenand_init(BlockDriverState *bdrv, uint32_t id,
+ int regshift, qemu_irq irq);
void *onenand_raw_otp(void *opaque);
/* ecc.c */
diff --git a/hw/nseries.c b/hw/nseries.c
index 45b52bb..96cc490 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -31,6 +31,7 @@
#include "hw.h"
#include "bt.h"
#include "loader.h"
+#include "blockdev.h"
/* Nokia N8x0 support */
struct n800_s {
@@ -163,13 +164,14 @@ static const uint8_t n8x0_cal_bt_id[] = {
static void n8x0_nand_setup(struct n800_s *s)
{
char *otp_region;
+ DriveInfo *dinfo;
+ dinfo = drive_get(IF_MTD, 0, 0);
/* Either ec40xx or ec48xx are OK for the ID */
+ s->nand = onenand_init(dinfo ? dinfo->bdrv : 0, 0xec4800, 1,
+ qdev_get_gpio_in(s->cpu->gpio, N8X0_ONENAND_GPIO));
omap_gpmc_attach(s->cpu->gpmc, N8X0_ONENAND_CS, 0, onenand_base_update,
- onenand_base_unmap,
- (s->nand = onenand_init(0xec4800, 1,
- qdev_get_gpio_in(s->cpu->gpio,
- N8X0_ONENAND_GPIO))));
+ onenand_base_unmap, s->nand);
otp_region = onenand_raw_otp(s->nand);
memcpy(otp_region + 0x000, n8x0_cal_wlan_mac, sizeof(n8x0_cal_wlan_mac));
diff --git a/hw/onenand.c b/hw/onenand.c
index 71c1ab4..3a19d7f 100644
--- a/hw/onenand.c
+++ b/hw/onenand.c
@@ -615,10 +615,10 @@ static CPUWriteMemoryFunc * const onenand_writefn[] = {
onenand_write,
};
-void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
+void *onenand_init(BlockDriverState *bdrv, uint32_t id,
+ int regshift, qemu_irq irq)
{
OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
- DriveInfo *dinfo = drive_get(IF_MTD, 0, 0);
uint32_t size = 1 << (24 + ((id >> 12) & 7));
void *ram;
@@ -632,11 +632,13 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq
irq)
s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(onenand_readfn,
onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
- if (!dinfo)
+ s->bdrv = bdrv;
+ if (!s->bdrv) {
s->image = memset(qemu_malloc(size + (size >> 5)),
- 0xff, size + (size >> 5));
- else
- s->bdrv = dinfo->bdrv;
+ 0xff, size + (size >> 5));
+ } else {
+ s->bdrv_cur = s->bdrv;
+ }
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);
--
1.7.1
- Re: [Qemu-devel] [PATCH 02/15] hw/omap_gpio.c: Don't complain about some writes to r/o registers, (continued)
- [Qemu-devel] [PATCH 11/15] hw/nand: qdevify, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 15/15] hw/onenand: program actions can only clear bits, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 09/15] hw/nand: Support multiple reads following READ STATUS, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 13/15] onenand: Handle various ID fields separately, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 04/15] hw/omap_gpio.c: Convert to qdev, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 07/15] hw/nand: Support large NAND devices, Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 05/15] lm832x: Take DeviceState pointer in lm832x_key_event(), Peter Maydell, 2011/07/29
- [Qemu-devel] [PATCH 12/15] onenand: Pass BlockDriverState to init function,
Peter Maydell <=
- [Qemu-devel] [PATCH 03/15] hw/omap_clk: Add the clock for the OMAP2430-specific fifth GPIO module, Peter Maydell, 2011/07/29