Re: [Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC

[Scott Wood]

On Fri, 22 Jul 2011 17:01:11 +0200
Alexander Graf <address@hidden> wrote:

> On 22.07.2011, at 16:08, Elie Richa wrote:
> 
> > > #if MAX_IPI > 0
> > >     case 0x40: /* IDE */
> > >     case 0x50:
> > >         idx = (addr - 0x40) >> 4;
> > >         retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
> > >         break;
> > > #endif
> > 
> > These are the IPI dispatch registers which are write only, so I suppose 
> > this shouldn't be here right?
> 
> The code was there long before me :). No idea why it is there though - it 
> tries to read out the IDE register for 2 IPIs. Maybe it was read-write in 
> early versions of MPIC? Scott, any idea?

I don't know about early MPICs, but I don't know how you'd even define that
register for read -- it's a command, not state.

I suspect it's just a bug -- especially given the initialization to 1,
which suggests the author saw it as just another destination register.

-Scott