[Qemu-devel] [Bug 812398] [NEW] powerpc 7450 MMU initialization broken

[till]

Public bug reported:

The 7540 family of PPCs' MMU can update TLBs using hardware search (like
a 604 or 7400) but also using a software algorithm. The mechanism used
is defined by HID0[STEN].

By default (CPU reset) HID0 is set to 0x80000000 (BTW; another small bug, qemu 
doesn't set the hardwired MSB), hence
the software-table lookup feature is *disabled*. However, the default (and 
immutable) 'mmu_model' for this CPU family is POWERC_MMU_SOFT_74XX which choses 
the soft TLB replacement scheme.

To fix this:

1) the initial mmu_model for the 7450 family (includes 7441, 7445, 7451, 7455, 
7457, 7447, 7448) should be: POWERPC_MMU_32B
2) when HID0[STEN] is written then the mmu_model should be changed accordingly 
(I'm not familiar enough with the qemu internal state to judge if any cached 
state would have to be updated).

** Affects: qemu
     Importance: Undecided
         Status: New

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https://bugs.launchpad.net/bugs/812398

Title:
  powerpc 7450 MMU initialization broken

Status in QEMU:
  New

Bug description:
  The 7540 family of PPCs' MMU can update TLBs using hardware search
  (like a 604 or 7400) but also using a software algorithm. The
  mechanism used is defined by HID0[STEN].

  By default (CPU reset) HID0 is set to 0x80000000 (BTW; another small bug, 
qemu doesn't set the hardwired MSB), hence
  the software-table lookup feature is *disabled*. However, the default (and 
immutable) 'mmu_model' for this CPU family is POWERC_MMU_SOFT_74XX which choses 
the soft TLB replacement scheme.

  To fix this:

  1) the initial mmu_model for the 7450 family (includes 7441, 7445, 7451, 
7455, 7457, 7447, 7448) should be: POWERPC_MMU_32B
  2) when HID0[STEN] is written then the mmu_model should be changed 
accordingly (I'm not familiar enough with the qemu internal state to judge if 
any cached state would have to be updated).

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