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[Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium

From: khansa
Subject: [Qemu-devel] [PATCH 0/3] MIPS64 user mode emulation in QEMU with Cavium specific instruction support
Date: Tue, 5 Jul 2011 14:19:25 +0500

From: Khansa Butt <address@hidden>

This is the team work of Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt 
from HPCN Lab KICS UET Lahore. 
Cavium Networks's Octeon processors are based on MIPS64r2 
We have Implemented 27 user mode Cavium specific instructions. 
Richard Henderson told me that QEMU does not support 64-bit 
address spaces in user mode from a 32-bit host. so this code will work 
only on  64 bit host. Although we did some workaround to run MIPS64 on 32 x86
and it can be generlized for other architectures. We will submit that after 
submission. This development work is tested for 64 bit X86 and working fine 
all Cavium specific instructions are also tested. teast cases can be provided 
if required.
Octeon binaries (ELF) can be downloaded from below links
If you have any objection regarding the Implementation of 
Cavium instructions please read following notes. 


The detail of some instructions are as follows 
1)seq rd,rs,rt 
seq-->rd = 1 if rs = rt 
is equivalent to 
xor rd,rs,rt 
sltiu rd,rd,1 
2)exts rt,rs,p,lenm1 
rt = sign-extend(rs<p+lenm1:p>,lenm1) 
>From reference manual of Cavium Networks 
"Bit locations p + lenm1 to p are extracted from rs and the result is written 
into the 
lowest bits of destination register rt. The remaining bits in rt are a 
sign-extension of 
the most-significant bit of the bit field (i.e. rt<63:lenm1> are all duplicates 
of the 
source-register bit rs<p+lenm1>)." so we can't use any of 8,16 or 32 bit 
sign extention tcg function. To sign extend according to msb of bit field 
we have our own implementation
3)dmul rd,rs,rt 
This instruction is included in gen_arith() because it is three operand 
double word multiply instruction.


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