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[Qemu-devel] [RHEL6 qemu-kvm PATCH 08/11] reorder cpuid feature bits on
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [RHEL6 qemu-kvm PATCH 08/11] reorder cpuid feature bits on target-x86_64.conf |
Date: |
Thu, 2 Jun 2011 16:13:07 -0300 |
This makes the flag order match the bit order in the CPU. This patch just
changes the ordering on the config file, and should have no visible effect.
This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <address@hidden>,
<http://marc.info/?l=qemu-devel&m=130618871926030>.
To make sure the flag sets are really not changed by this patch, I have
used the following stupid script to compare the flag values in the
config files:
https://gist.github.com/1004885
Signed-off-by: Eduardo Habkost <address@hidden>
---
sysconfigs/target/target-x86_64.conf | 32 ++++++++++++++++----------------
1 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/sysconfigs/target/target-x86_64.conf
b/sysconfigs/target/target-x86_64.conf
index ea310bb..d368b6c 100644
--- a/sysconfigs/target/target-x86_64.conf
+++ b/sysconfigs/target/target-x86_64.conf
@@ -7,8 +7,8 @@
family = "6"
model = "15"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 ssse3 x2apic"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "x2apic ssse3 sse3"
extfeature_edx = "i64 syscall xd"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
@@ -21,8 +21,8 @@
family = "6"
model = "23"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 ssse3 sse4.1 x2apic"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "x2apic sse4.1 cx16 ssse3 sse3"
extfeature_edx = "i64 syscall xd"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
@@ -35,8 +35,8 @@
family = "6"
model = "26"
stepping = "3"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 ssse3 sse4.1 sse4.2 popcnt x2apic"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "popcnt x2apic sse4.2 sse4.1 cx16 ssse3 sse3"
extfeature_edx = "i64 syscall xd"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
@@ -49,9 +49,9 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 x2apic" # x2apic kvm emulated
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu
lm syscall nx"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "x2apic sse3" # x2apic kvm emulated
+ extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr
tsc pse de fpu"
extfeature_ecx = " "
xlevel = "0x80000008"
model_id = "AMD Opteron 240 (Gen 1 Class Opteron)"
@@ -63,9 +63,9 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 x2apic" # x2apic kvm emulated
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu
lm syscall nx rdtscp"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "x2apic cx16 sse3" # x2apic kvm emulated
+ extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce
pae msr tsc pse de fpu"
extfeature_ecx = "svm lahf_lm"
xlevel = "0x80000008"
model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)"
@@ -77,10 +77,10 @@
family = "15"
model = "6"
stepping = "1"
- feature_edx = "sse2 sse fxsr mmx pat cmov pge sep apic cx8 mce pae msr tsc
pse de fpu mtrr clflush mca pse36"
- feature_ecx = "sse3 cx16 monitor popcnt x2apic" # x2apic kvm emulated
- extfeature_edx = "fxsr mmx pat cmov pge apic cx8 mce pae msr tsc pse de fpu
lm syscall nx rdtscp"
- extfeature_ecx = "svm sse4a abm misalignsse lahf_lm"
+ feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep
apic cx8 mce pae msr tsc pse de fpu"
+ feature_ecx = "popcnt x2apic cx16 monitor sse3" # x2apic kvm emulated
+ extfeature_edx = "lm rdtscp fxsr mmx nx pat cmov pge syscall apic cx8 mce
pae msr tsc pse de fpu"
+ extfeature_ecx = "misalignsse sse4a abm svm lahf_lm"
xlevel = "0x80000008"
model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)"
--
1.7.3.2
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 00/11] cpu model bug fixes and definition corrections (v2), Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 02/11] Allow an optional qemu_early_init_vcpu(), Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 05/11] cpu defs: use Intel flag names for Intel models, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 08/11] reorder cpuid feature bits on target-x86_64.conf,
Eduardo Habkost <=
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 04/11] Support -readconfig "?" to debug config file loading, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 03/11] Add kvm emulated x2apic flag to config defined cpu models (v2), Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 01/11] correct archaic CPU model "model" field for Intel CPUs., Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 09/11] cpu defs: add pse36, mca, mtrr to AMD CPU definitions, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 10/11] add Westmere as a qemu cpu model, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 07/11] cpu defs: uncomment empty extfeatures_ecx definition for Opteron_G1, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 11/11] add "default" pseudo CPU model name, Eduardo Habkost, 2011/06/02
- [Qemu-devel] [RHEL6 qemu-kvm PATCH 06/11] cpu defs: remove replicated flags from Intel, Eduardo Habkost, 2011/06/02
- Re: [Qemu-devel] [PATCH 00/11] cpu model bug fixes and definition corrections (v2), Eduardo Habkost, 2011/06/02