Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata]

On Wed, May 25, 2011 at 09:15:55AM +0200, Jan Kiszka wrote:
> FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
> accessing the chip_config registers appears to rely on the host being
> little endian (direct memcpy).
> 
> In contrast, the PCI mapping issue turned out to be a read herring. The
> unmapped regions were actually ROM BARs which are usually unmapped. And
> the network issues were related to an outdated DSDT. Somehow rebuilding
> Seabios did not always properly regenerate them, so my polarity fixes
> were not inluded. Haven't looked into details, but deleting out/ and
> src/*.hex resolved that.

Good catch. I queued it in my repo.


> 
> I'll have to put this topic aside for now as it looks like we don't
> depend on it for PCIe pass-through. Still, it's a cool thing, and I
> would be happy to find it upstream soon!
> 
> Jan
> 
> ------8<-------
> 
> From: Jan Kiszka <address@hidden>
> Subject: [PATCH] q35: Fix irr initialization for slots 25..31
> 
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
> 
> Signed-off-by: Jan Kiszka <address@hidden>
> ---
>  hw/q35.c |   10 +++++++---
>  1 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/q35.c b/hw/q35.c
> index a06ea7d..0ab8532 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -424,14 +424,18 @@ static void ich9_cc_update_ir(uint8_t 
> irr[PCI_NUM_PINS], uint32_t ir)
>  static void ich9_cc_update(ICH9_LPCState *lpc)
>  {
>      int slot;
> -    int reg_offset;
> +    int reg;
>      int intx;
>  
>      /* D{25 - 31}IR, but D30IR is read only to 0. */
> -    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> +    for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
>          if (slot != 30) {
>              ich9_cc_update_ir(lpc->irr[slot],
> -                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> +                              lpc->chip_config[reg] |
> +                              (uint32_t)lpc->chip_config[reg + 1] << 8);
> +        }
> +        if (slot <= 27) {
> +            reg += 2;
>          }
>      }
>  
> -- 
> 1.7.1
> 



-- 
yamahata