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[Qemu-devel] [PATCH 1/9] cpu_loop_exit: avoid using AREG0
From: |
Blue Swirl |
Subject: |
[Qemu-devel] [PATCH 1/9] cpu_loop_exit: avoid using AREG0 |
Date: |
Sun, 22 May 2011 14:17:28 +0300 |
Make cpu_loop_exit() take a parameter for CPUState instead of relying
on global env.
Signed-off-by: Blue Swirl <address@hidden>
---
cpu-exec.c | 16 ++++++++--------
exec-all.h | 2 +-
hw/alpha_palcode.c | 2 +-
target-alpha/op_helper.c | 4 ++--
target-arm/op_helper.c | 6 +++---
target-cris/op_helper.c | 4 ++--
target-i386/op_helper.c | 16 ++++++++--------
target-lm32/op_helper.c | 6 +++---
target-m68k/op_helper.c | 6 +++---
target-microblaze/op_helper.c | 4 ++--
target-mips/op_helper.c | 4 ++--
target-ppc/op_helper.c | 2 +-
target-sh4/op_helper.c | 10 +++++-----
target-sparc/op_helper.c | 6 +++---
target-unicore32/op_helper.c | 2 +-
user-exec.c | 11 ++++++-----
16 files changed, 51 insertions(+), 50 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 6ddd8dd..caf0dbe 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -38,10 +38,10 @@ int qemu_cpu_has_work(CPUState *env)
return cpu_has_work(env);
}
-void cpu_loop_exit(void)
+void cpu_loop_exit(CPUState *env1)
{
- env->current_tb = NULL;
- longjmp(env->jmp_env, 1);
+ env1->current_tb = NULL;
+ longjmp(env1->jmp_env, 1);
}
/* exit the current TB from a signal handler. The host registers are
@@ -328,7 +328,7 @@ int cpu_exec(CPUState *env1)
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
@@ -337,7 +337,7 @@ int cpu_exec(CPUState *env1)
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#endif
#if defined(TARGET_I386)
@@ -345,7 +345,7 @@ int cpu_exec(CPUState *env1)
svm_check_intercept(SVM_EXIT_INIT);
do_cpu_init(env);
env->exception_index = EXCP_HALTED;
- cpu_loop_exit();
+ cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(env);
} else if (env->hflags2 & HF2_GIF_MASK) {
@@ -538,7 +538,7 @@ int cpu_exec(CPUState *env1)
if (unlikely(env->exit_request)) {
env->exit_request = 0;
env->exception_index = EXCP_INTERRUPT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@@ -621,7 +621,7 @@ int cpu_exec(CPUState *env1)
}
env->exception_index = EXCP_INTERRUPT;
next_tb = 0;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
}
}
diff --git a/exec-all.h b/exec-all.h
index cf3a704..1862428 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -91,7 +91,7 @@ TranslationBlock *tb_gen_code(CPUState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUState *env);
-void QEMU_NORETURN cpu_loop_exit(void);
+void QEMU_NORETURN cpu_loop_exit(CPUState *env1);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
diff --git a/hw/alpha_palcode.c b/hw/alpha_palcode.c
index 033b542..49719f6 100644
--- a/hw/alpha_palcode.c
+++ b/hw/alpha_palcode.c
@@ -96,7 +96,7 @@ static void do_swappal (CPUState *env, uint64_t palid)
env->pal_handler = NULL;
env->ipr[IPR_PAL_BASE] = palid;
env->pc = env->ipr[IPR_PAL_BASE];
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
}
diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c
index 4ccb10b..d50977c 100644
--- a/target-alpha/op_helper.c
+++ b/target-alpha/op_helper.c
@@ -29,7 +29,7 @@ void QEMU_NORETURN helper_excp (int excp, int error)
{
env->exception_index = excp;
env->error_code = error;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
uint64_t helper_load_pcc (void)
@@ -1378,7 +1378,7 @@ void tlb_fill (target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
}
}
/* Exception index and error code are already set */
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 8334fbc..4635884 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -25,7 +25,7 @@
void raise_exception(int tt)
{
env->exception_index = tt;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
@@ -234,13 +234,13 @@ void HELPER(wfi)(void)
{
env->exception_index = EXCP_HLT;
env->halted = 1;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
uint32_t HELPER(cpsr_read)(void)
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 34329e2..b3ddd33 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -83,7 +83,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
helper_top_evaluate_flags();
}
}
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
@@ -93,7 +93,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_tlb_flush_pid(uint32_t pid)
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 3c539f3..b7e0304 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -1017,7 +1017,7 @@ void helper_syscall(int next_eip_addend)
{
env->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#else
void helper_syscall(int next_eip_addend)
@@ -1352,7 +1352,7 @@ static void QEMU_NORETURN raise_interrupt(int
intno, int is_int, int error_code,
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
/* shortcuts to generate exceptions */
@@ -4721,7 +4721,7 @@ static void do_hlt(void)
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_hlt(int next_eip_addend)
@@ -4759,7 +4759,7 @@ void helper_mwait(int next_eip_addend)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_reset_rf(void)
@@ -5111,7 +5111,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_EXEPT:
env->exception_index = vector;
@@ -5119,7 +5119,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = -1;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_SOFT:
env->exception_index = vector;
@@ -5127,7 +5127,7 @@ void helper_vmrun(int aflag, int next_eip_addend)
env->exception_is_int = 1;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n",
env->exception_index, env->error_code);
@@ -5463,7 +5463,7 @@ void helper_vmexit(uint32_t exit_code, uint64_t
exit_info_1)
env->error_code = 0;
env->old_exception = -1;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#endif
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index c72b1df..a34cecd 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -20,14 +20,14 @@
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_hlt(void)
{
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_wcsr_im(uint32_t im)
@@ -98,7 +98,7 @@ void tlb_fill(target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 9b13bdb..084a182 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -71,7 +71,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
@@ -118,7 +118,7 @@ void do_interrupt(int is_hw)
}
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
return;
}
if (env->exception_index >= EXCP_TRAP0
@@ -160,7 +160,7 @@ void do_interrupt(int is_hw)
static void raise_exception(int tt)
{
env->exception_index = tt;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void HELPER(raise_exception)(uint32_t tt)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index c7b2f97..1a0a476 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -63,7 +63,7 @@ void tlb_fill (target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
cpu_restore_state(tb, env, pc);
}
}
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
@@ -107,7 +107,7 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(uint32_t index)
{
env->exception_index = index;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_debug(void)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index b8e4991..6b966b1 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -38,7 +38,7 @@ void helper_raise_exception_err (uint32_t exception,
int error_code)
#endif
env->exception_index = exception;
env->error_code = error_code;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_raise_exception (uint32_t exception)
@@ -277,7 +277,7 @@ static inline target_phys_addr_t
do_translate_address(target_ulong address, int
lladdr = cpu_mips_translate_address(env, address, rw);
if (lladdr == -1LL) {
- cpu_loop_exit();
+ cpu_loop_exit(env);
} else {
return lladdr;
}
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index c52a371..4b409b9 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -44,7 +44,7 @@ void helper_raise_exception_err (uint32_t exception,
uint32_t error_code)
#endif
env->exception_index = exception;
env->error_code = error_code;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_raise_exception (uint32_t exception)
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index b909d18..a932225 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -66,7 +66,7 @@ void tlb_fill(target_ulong addr, int is_write, int
mmu_idx, void *retaddr)
if (ret) {
/* now we have a real cpu fault */
cpu_restore_state_from_retaddr(retaddr);
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
@@ -87,7 +87,7 @@ static inline void raise_exception(int index, void *retaddr)
{
env->exception_index = index;
cpu_restore_state_from_retaddr(retaddr);
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_raise_illegal_instruction(void)
@@ -113,7 +113,7 @@ void helper_raise_slot_fpu_disable(void)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_sleep(uint32_t next_pc)
@@ -122,7 +122,7 @@ void helper_sleep(uint32_t next_pc)
env->in_sleep = 1;
env->exception_index = EXCP_HLT;
env->pc = next_pc;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_trapa(uint32_t tra)
@@ -482,7 +482,7 @@ static void update_fpscr(void *retaddr)
if (cause & enable) {
cpu_restore_state_from_retaddr(retaddr);
env->exception_index = 0x120;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
}
}
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index b38691e..491a9f3 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -316,7 +316,7 @@ static inline target_ulong asi_address_mask(CPUState *env1,
static void raise_exception(int tt)
{
env->exception_index = tt;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void HELPER(raise_exception)(int tt)
@@ -3702,7 +3702,7 @@ void helper_ldxfsr(uint64_t new_fsr)
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#ifndef TARGET_SPARC64
@@ -4402,7 +4402,7 @@ void tlb_fill(target_ulong addr, int is_write,
int mmu_idx, void *retaddr)
ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (ret) {
cpu_restore_state2(retaddr);
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
env = saved_env;
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 31e4b11..541e6f0 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -16,7 +16,7 @@
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
static target_ulong asr_read(void)
diff --git a/user-exec.c b/user-exec.c
index d4a6abb..02c2f8b 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -37,13 +37,14 @@
//#define DEBUG_SIGNAL
+static void exception_action(CPUState *env1)
+{
#if defined(TARGET_I386)
-#define EXCEPTION_ACTION \
- raise_exception_err(env->exception_index, env->error_code)
+ raise_exception_err(env1->exception_index, env1->error_code);
#else
-#define EXCEPTION_ACTION \
- cpu_loop_exit()
+ cpu_loop_exit(env1);
#endif
+}
/* exit the current TB from a signal handler. The host registers are
restored in a state compatible with the CPU emulator
@@ -118,7 +119,7 @@ static inline int handle_cpu_signal(unsigned long
pc, unsigned long address,
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
- EXCEPTION_ACTION;
+ exception_action(env);
/* never comes here */
return 1;
--
1.6.2.4
0001-cpu_loop_exit-avoid-using-AREG0.patch
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