Re: [Qemu-devel] [RFC] Memory API

[Jan Kiszka]

On 2011-05-20 09:23, Gleb Natapov wrote:
> On Thu, May 19, 2011 at 08:55:49PM +0200, Jan Kiszka wrote:
>>>>>> Because we should catch accidental overlaps in all those non PCI devices
>>>>>> with hard-wired addressing. That's a bug in the device/machine model and
>>>>>> should be reported as such by QEMU.
>>>>> Why should we complicate API to catch unlikely errors? If you want to
>>>>> debug that add capability to dump memory map from the monitor.
>>>>
>>>> Because we need to switch tons of code that so far saw a fairly
>>>> different reaction of the core to overlapping regions.
>>>>
>>> How so? Today if there is accidental overlap device will not function 
>>> properly.
>>> With new API it will be the same.
>>
>> I rather expect subtle differences as overlapping registration changes
>> existing regions, in the future those will recover.
>>
> Where do you expect the differences will come from? Conversion to the new
> API shouldn't change the order of the registration and if the last
> registration will override previous one the end result should be the
> same as we have today.

A) Removing regions will change significantly. So far this is done by
setting a region to IO_MEM_UNASSIGNED, keeping truncation. With the new
API that will be a true removal which will additionally restore hidden
regions.

B) Uncontrolled overlapping is a bug that should be caught by the core,
and a new API is a perfect chance to do this.

> 
>>>>>>>> new region management will not cause any harm to overlapping regions so
>>>>>>>> that they can "recover" when the overlap is gone.
>>>>>>>>
>>>>>>>>>
>>>>>>>>> Another example may be APIC region and PCI. They overlap, but neither
>>>>>>>>> CPU nor PCI knows about it.
>>>>>>>>
>>>>>>>> And they do not need to. The APIC regions will be managed by the 
>>>>>>>> per-CPU
>>>>>>>> region management, reusing the tool box we need for all bridges. It 
>>>>>>>> will
>>>>>>>> register the APIC page with a priority higher than the default one, 
>>>>>>>> thus
>>>>>>>> overriding everything that comes from the host bridge. I think that
>>>>>>>> reflects pretty well real machine behaviour.
>>>>>>>>
>>>>>>> What is "higher"? How does it know that priority is high enough?
>>>>>>
>>>>>> Because no one else manages priorities at a specific hierarchy level.
>>>>>> There is only one.
>>>>>>
>>>>> PCI and CPU are on different hierarchy levels. PCI is under the PIIX and
>>>>> CPU is on a system BUS.
>>>>
>>>> The priority for the APIC mapping will be applied at CPU level, of
>>>> course. So it will override everything, not just PCI.
>>>>
>>> So you do not need explicit priority because the place in hierarchy
>>> implicitly provides you with one.
>>
>> Yes.
> OK :) So you agree that we can do without priorities :)

Nope, see below how your own example depends on them.

> 
>>       Alternatively, you could add a prio offset to all mappings when
>> climbing one level up, provided that offset is smaller than the prio
>> range locally available to each level.
>>
> Then a memory region final priority will depend on a tree height. If two
> disjointed tree branches of different height will claim the same memory
> region the higher one will have higher priority. I think this priority
> management is a can of worms.

It is not as it remains a pure local thing and helps implementing the
sketched scenarios. Believe, I tried to fix PAM/SMRAM already.

> 
> Only the lowest level (aka system bus) will use memory API directly.

Not necessarily. It depends on how much added value buses like PCI or
ISA or whatever can offer for managing I/O regions. For some purposes,
it may as well be fine to just call the memory_* service directly and
pass the result of some operation to the bus API later on.

> PCI
> device will call PCI subsystem. PCI subsystem, instead of assigning
> arbitrary priorities to all overlappings,

Again: PCI will _not_ assign arbitrary priorities but only
MEMORY_REGION_DEFAULT_PRIORITY, likely 0.

> may just resolve them and pass
> flattened view to the chipset. Chipset in turn will look for overlappings
> between PCI memory areas and RAM/ISA/other memory areas that are outside
> of PCI windows and resolve all those passing the flattened view to system
> bus where APIC/PCI conflict will be resolved and finally memory API will
> be used to create memory map. In such a model I do not see the need for
> priorities. All overlappings are resolved in the most logical place,
> the one that has the best knowledge about how to resolve the conflict.
> The will be no code duplication. Overlapping resolution code will be in
> separate library used by all layers.

That does not specify how the PCI bridge or the chipset will tell that
overlapping resolution lib _how_ overlapping regions shall be translated
into a flat representation. And precisely here come priorities into
play. It is the way to tell that lib either "region A shall override
region B" if A has higher prio or "if region A and B overlap, do
whatever you want" if both have the same prio.

Jan

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