[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [RFC] Memory API
From: |
Jan Kiszka |
Subject: |
Re: [Qemu-devel] [RFC] Memory API |
Date: |
Thu, 19 May 2011 20:21:15 +0200 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 |
On 2011-05-19 20:06, Anthony Liguori wrote:
> On 05/19/2011 08:55 AM, Avi Kivity wrote:
>> On 05/19/2011 04:50 PM, Anthony Liguori wrote:
>>>
>>> But the i440fx doesn't register the VGA region. The PIIX3 (ISA bus)
>>> does, so how does it know what the priority of that mapping is?
>>>
>>
>> The PCI bridge also has a say, no?
>
> For legacy VGA memory? That's a good question. I've always assumed
> that legacy VGA memory is handled directly in the chipset by redirecting
> writes to the first VGA adapter it encounters (which usually happens to
> be the builtin one these days).
Nope. It's well defined in the PCI specs that every PCI-PCI bridge can
(or have to? need to check) control the flow of legacy VGA to its
downstream devices.
>
> I'm not sure it's possible to have a VGA device behind a bridge that
> also handles legacy VGA memory because the bridge pretty clearly can
> only have BARs within a certain region of memory (based on the bridge's
> config space).
That's part of my notebook PCI tree, I bet you have something similar:
\-[0000:00]-+-00.0 Intel Corporation Core Processor DRAM Controller
+-01.0-[01]--+-00.0 nVidia Corporation GT216 [Quadro FX 880M]
| \-00.1 nVidia Corporation High Definition Audio
Controller
So even this single, though not built-in VGA adapter is behind a bridge.
And if you look closer, you can find:
00:01.0 PCI bridge: Intel Corporation Core Processor PCI Express x16 Root Port
(rev 02) (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
Stepping- SERR- FastB2B- DisINTx+
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00002000-00002fff
Memory behind bridge: cc000000-cdefffff
Prefetchable memory behind bridge: 00000000ce000000-00000000dfffffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort-
<MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
...
Note that 'VGA+' in BridgeCtl. It allows the NVIDIA adapter to handle
legacy VGA.
Jan
signature.asc
Description: OpenPGP digital signature
- Re: [Qemu-devel] [RFC] Memory API, (continued)
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Jan Kiszka, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Jan Kiszka, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API,
Jan Kiszka <=
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Edgar E. Iglesias, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Peter Maydell, 2011/05/19
- Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/18
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/18
- Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/18
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/18
- Re: [Qemu-devel] [RFC] Memory API, Jan Kiszka, 2011/05/18
- Re: [Qemu-devel] [RFC] Memory API, Avi Kivity, 2011/05/18
Re: [Qemu-devel] [RFC] Memory API, Anthony Liguori, 2011/05/18