[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 2/3] target-mips:Support for Cavium-Octeon speci
|
From: |
Andreas Färber |
|
Subject: |
Re: [Qemu-devel] [PATCH 2/3] target-mips:Support for Cavium-Octeon specific instructions |
|
Date: |
Tue, 17 May 2011 01:21:03 +0200 |
Am 29.04.2011 um 08:19 schrieb Khansa Butt:
From f699dbfdca62c5af92d764673b2300131d26263e Mon Sep 17 00:00:00 2001
From: Ehsan-ul-Haq, Abdul Qadeer, Abdul Waheed, Khansa Butt <address@hidden
>
Date: Wed, 27 Apr 2011 16:08:16 +0500
Subject: [PATCH 2/3] target-mips:Support for Cavium-Octeon specific
instructions
These headers, except for From:, shouldn't turn up here. It looks as
if the message was HTML-formatted, too. Same issue with the other two.
Use git-send-email to avoid this, so that the patch can be processed.
Space after the colon in the subject, please. :)
Further patch description is missing?
Signed-off-by: Khansa Butt <address@hidden>
This is the first time I'm seeing multiple people in From:. I would
rather expect only you in the From: and multiple Signed-off-by: lines
here... Maybe one of the Linux gurus can enlighten us?
---
host-utils.c | 1 +
target-mips/cpu.h | 7 +
target-mips/helper.h | 5 +
target-mips/op_helper.c | 62 +++++++
target-mips/translate.c | 445 +++++++++++++++++++++++++++++++++++++
++++++++--
5 files changed, 509 insertions(+), 11 deletions(-)
diff --git a/host-utils.c b/host-utils.c
index dc96123..1128698 100644
--- a/host-utils.c
+++ b/host-utils.c
@@ -102,4 +102,5 @@ void muls64 (uint64_t *plow, uint64_t *phigh,
int64_t a, int64_t b)
a, b, *phigh, *plow);
#endif
}
+
#endif /* !defined(__x86_64__) */
Please remove this unnecessary whitespace change from the patch series.
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 297ab64..e892d39 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -8,7 +8,12 @@ DEF_HELPER_3(ldl, tl, tl, tl, int)
DEF_HELPER_3(ldr, tl, tl, tl, int)
DEF_HELPER_3(sdl, void, tl, tl, int)
DEF_HELPER_3(sdr, void, tl, tl, int)
+DEF_HELPER_2(v3mulu, tl, tl, tl)
+DEF_HELPER_2(vmulu, tl, tl, tl)
+DEF_HELPER_1(dpop, tl, tl)
#endif
+DEF_HELPER_1(pop, tl, tl);
The other ones don't end with semicolon?
+
DEF_HELPER_3(lwl, tl, tl, tl, int)
DEF_HELPER_3(lwr, tl, tl, tl, int)
DEF_HELPER_3(swl, void, tl, tl, int)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index b8e4991..96cfbe6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -266,7 +266,69 @@ void helper_dmultu (target_ulong arg1,
target_ulong arg2)
{
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1,
arg2);
}
I would expect an empty line between functions.
+static void addc(uint64_t res[], uint64_t a, int i)
+{
+ uint64_t c = res[i];
+ for (; i < 4; i++) {
+ res[i] = c + a;
+ if (res[i] < a) {
+ c = 1;
+ a = res[i+1];
+ } else
Coding style.
+ break;
+ }
+}
Line?
+target_ulong helper_v3mulu(target_ulong arg1, target_ulong arg2)
+{
+ uint64_t hi, lo, res[4];
+ int i;
+ for (i = 0; i < 4; i++) {
+ res[i] = 0;
+ }
+ mulu64(&res[0], &res[1], env->active_tc.MPL0, arg1);
+ mulu64(&lo, &hi, env->active_tc.MPL1, arg1);
+ res[1] = res[1] + lo;
+ if (res[1] < lo)
Coding Style.
+ res[2]++;
+ res[2] = res[2] + hi;
+ if (res[2] < hi)
Dito. More skipped, try using the checkpatch script.
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c88c3f9..cb431a8 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -70,6 +70,11 @@ enum {
OPC_JAL = (0x03 << 26),
OPC_JALS = OPC_JAL | 0x5,
OPC_BEQ = (0x04 << 26), /* Unconditional if rs = rt = 0
(B) */
+ /* Cavium Specific */
This seems misleading to me: Probably only the ones inserted are
Cavium-specific but not OPC_BEQL etc.?
+ OPC_BBIT1 = (0x3a << 26), /* jump on bit set, cavium
specific */
+ OPC_BBIT132 = (0x3e << 26), /* jump on bit set(for upper 32
bits) */
+ OPC_BBIT0 = (0x32 << 26), /* jump on bit clear, cavium
specific */
+ OPC_BBIT032 = (0x36 << 26), /* jump on bit clear(for upper 32
bits) */
OPC_BEQL = (0x14 << 26),
OPC_BNE = (0x05 << 26),
OPC_BNEL = (0x15 << 26),
@@ -265,6 +270,31 @@ enum {
OPC_MADD = 0x00 | OPC_SPECIAL2,
OPC_MADDU = 0x01 | OPC_SPECIAL2,
OPC_MUL = 0x02 | OPC_SPECIAL2,
+ /* Cavium Specific Instructions */
+ OPC_BADDU = 0x28 | OPC_SPECIAL2,
+ OPC_DMUL = 0x03 | OPC_SPECIAL2,
+ OPC_EXTS = 0x3a | OPC_SPECIAL2,
+ OPC_EXTS32 = 0x3b | OPC_SPECIAL2,
+ OPC_CINS = 0x32 | OPC_SPECIAL2,
+ OPC_CINS32 = 0x33 | OPC_SPECIAL2,
+ OPC_SEQI = 0x2e | OPC_SPECIAL2,
+ OPC_SNEI = 0x2f | OPC_SPECIAL2,
+ OPC_MTM0 = 0x08 | OPC_SPECIAL2,
+ OPC_MTM1 = 0x0c | OPC_SPECIAL2,
+ OPC_MTM2 = 0x0d | OPC_SPECIAL2,
+ OPC_MTP0 = 0x09 | OPC_SPECIAL2,
+ OPC_MTP1 = 0x0a | OPC_SPECIAL2,
+ OPC_MTP2 = 0x0b | OPC_SPECIAL2,
+ OPC_V3MULU = 0x11 | OPC_SPECIAL2,
+ OPC_VMM0 = 0x10 | OPC_SPECIAL2,
+ OPC_VMULU = 0x0f | OPC_SPECIAL2,
+ OPC_POP = 0X2C | OPC_SPECIAL2,
+ OPC_DPOP = 0X2D | OPC_SPECIAL2,
+ OPC_SEQ = 0x2a | OPC_SPECIAL2,
+ OPC_SNE = 0x2b | OPC_SPECIAL2,
+ OPC_SAA = 0x18 | OPC_SPECIAL2,
+ OPC_SAAD = 0x19 | OPC_SPECIAL2,
+/**************************************/
Missing indentation intentional?
OPC_MSUB = 0x04 | OPC_SPECIAL2,
OPC_MSUBU = 0x05 | OPC_SPECIAL2,
/* Loongson 2F */
@@ -483,7 +513,7 @@ enum {
static TCGv_ptr cpu_env;
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC],
cpu_ACX[MIPS_DSP_ACC];
-static TCGv cpu_dspctrl, btarget, bcond;
+static TCGv cpu_dspctrl, btarget, bcond, mpl0, mpl1, mpl2, p0, p1,
p2;
static TCGv_i32 hflags;
static TCGv_i32 fpu_fcr0, fpu_fcr31;
@@ -1419,7 +1449,30 @@ static void gen_arith_imm (CPUState *env,
DisasContext *ctx, uint32_t opc,
(void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt],
regnames[rs], uimm);
}
-
+#if defined(TARGET_MIPS64)
+/* set on equal immidiate/set if not equal immidiate */
immediate?
+static void gen_set_imm(CPUState *env, uint32_t opc,
+ int rt, int rs, int16_t imm)
+{
+ TCGv t0;
+ const char *opn = "imm set";
+ t0 = tcg_temp_new();
+ gen_load_gpr(t0, rs);
+ switch (opc) {
+ case OPC_SEQI:
+ tcg_gen_xori_tl(t0, t0, imm);
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, 1);
+ opn = "seqi";
+ break;
+ case OPC_SNEI:
+ tcg_gen_xori_tl(t0, t0, imm);
+ tcg_gen_setcondi_tl(TCG_COND_GT, cpu_gpr[rt], t0, 0);
+ opn = "snei";
+ break;
+ }
+ tcg_temp_free(t0);
+}
+#endif
/* Logic with immediate operand */
static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int
rs, int16_t imm)
{
@@ -11609,8 +11917,7 @@ static void decode_opc (CPUState *env,
DisasContext *ctx, int *is_branch)
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1, op2;
- int16_t imm;
-
Any reason to drop the empty line?
+ int16_t imm, imm10;
/* make sure instructions are on a word boundary */
if (ctx->pc & 0x3) {
env->CP0_BadVAddr = ctx->pc;
[...]
Andreas
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- Re: [Qemu-devel] [PATCH 2/3] target-mips:Support for Cavium-Octeon specific instructions,
Andreas Färber <=