[Qemu-devel] [PATCH] target-arm: fix LDMIA bug on page boundary

[오유연]

When consecutive memory locations are on page boundary, a base register may be
loaded before page fault occurs. After page fault handling, it losts the memory
location information. To solve this problem, loading a base register has to put 
back.

Signed-off-by: Yuyeon Oh <address@hidden>
---
 target-arm/translate.c |   18 +++++++++++++-----
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index e1bda57..61eb4d5 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7984,11 +7984,16 @@ static int disas_thumb2_insn(CPUState *env, 
DisasContext *s, uint16_t insn_hw1)
                         continue;
                     if (insn & (1 << 20)) {
                         /* Load.  */
-                        tmp = gen_ld32(addr, IS_USER(s));
-                        if (i == 15) {
-                            gen_bx(s, tmp);
-                        } else {
-                            store_reg(s, i, tmp);
+                        if (i == rn) {
+                            tmp2 = gen_ld32(addr, IS_USER(s));
+                        }
+                        else {
+                            tmp = gen_ld32(addr, IS_USER(s));
+                            if (i == 15) {
+                                gen_bx(s, tmp);
+                            } else {
+                                store_reg(s, i, tmp);
+                            }
                         }
                     } else {
                         /* Store.  */
@@ -7997,6 +8002,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext 
*s, uint16_t insn_hw1)
                     }
                     tcg_gen_addi_i32(addr, addr, 4);
                 }
+                if ((insn & (1 << 20)) && (insn & (1 << rn))) {
+                    store_reg(s, rn, tmp2);
+                }
                 if (insn & (1 << 21)) {
                     /* Base register writeback.  */
                     if (insn & (1 << 24)) {
-- 
1.7.4.msysgit.0