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[Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in GRLIB
From: |
Fabien Chouteau |
Subject: |
[Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in GRLIB IP Core User's Manual. |
Date: |
Mon, 3 Jan 2011 15:07:01 +0100 |
Signed-off-by: Fabien Chouteau <address@hidden>
---
hw/grlib_irqmp.c | 402 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 402 insertions(+), 0 deletions(-)
diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
new file mode 100644
index 0000000..9f947d1
--- /dev/null
+++ b/hw/grlib_irqmp.c
@@ -0,0 +1,402 @@
+/*
+ * QEMU GRLIB IRQMP Emulator
+ *
+ * (Multiprocessor and extended interrupt not supported)
+ *
+ * Copyright (c) 2010-2011 AdaCore
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "sysbus.h"
+#include "cpu.h"
+
+#include "grlib.h"
+
+//#define DEBUG_IRQ
+
+#ifdef DEBUG_IRQ
+#define DPRINTF(fmt, ...) \
+ do { printf("IRQMP: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)
+#endif
+
+#define IRQMP_MAX_CPU 16
+#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
+
+/* Memory mapped register offsets */
+#define LEVEL_OFFSET 0x00
+#define PENDING_OFFSET 0x04
+#define FORCE0_OFFSET 0x08
+#define CLEAR_OFFSET 0x0C
+#define MP_STATUS_OFFSET 0x10
+#define BROADCAST_OFFSET 0x14
+#define MASK_OFFSET 0x40
+#define FORCE_OFFSET 0x80
+#define EXTENDED_OFFSET 0xC0
+
+typedef struct IRQMPState IRQMPState;
+
+typedef struct IRQMP
+{
+ SysBusDevice busdev;
+
+ CPUSPARCState *env;
+
+ IRQMPState *state;
+} IRQMP;
+
+struct IRQMPState
+{
+ uint32_t level;
+ uint32_t pending;
+ uint32_t clear;
+ uint32_t broadcast;
+
+ uint32_t mask[IRQMP_MAX_CPU];
+ uint32_t force[IRQMP_MAX_CPU];
+ uint32_t extended[IRQMP_MAX_CPU];
+
+ IRQMP *parent;
+};
+
+static void grlib_irqmp_check_irqs(IRQMPState *state)
+{
+ assert(state != NULL);
+ CPUState *env = state->parent->env;
+ assert(env != NULL);
+
+ uint32_t pend = 0;
+ uint32_t level0 = 0;
+ uint32_t level1 = 0;
+
+
+ /* IRQ for CPU 0 (no SMP support) */
+ pend = (state->pending | state->force[0])
+ & state->mask[0];
+
+
+ level0 = pend & ~state->level;
+ level1 = pend & state->level;
+
+ DPRINTF("pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n",
+ state->pending, state->force[0],
+ state->mask[0], level1, level0);
+
+ /* Trigger level1 interrupt first and level0 if there is no level1 */
+ if (level1 != 0) {
+ env->pil_in = level1;
+ } else {
+ env->pil_in = level0;
+ }
+
+ if (env->pil_in && (env->interrupt_index == 0 ||
+ (env->interrupt_index & ~15) == TT_EXTINT)) {
+ unsigned int i;
+
+ for (i = 15; i > 0; i--) {
+ if (env->pil_in & (1 << i)) {
+ int old_interrupt = env->interrupt_index;
+
+ env->interrupt_index = TT_EXTINT | i;
+ if (old_interrupt != env->interrupt_index) {
+ DPRINTF("Set CPU IRQ %d\n", i);
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+ break;
+ }
+ }
+ } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
+ DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
+ env->interrupt_index = 0;
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+}
+
+void grlib_irqmp_ack(DeviceState *dev, int intno)
+{
+ assert(dev != NULL);
+
+ SysBusDevice *sdev = sysbus_from_qdev(dev);
+ assert(sdev != NULL);
+
+ IRQMP *irqmp = FROM_SYSBUS(typeof (*irqmp), sdev);
+ assert(irqmp != NULL);
+
+ IRQMPState *state = irqmp->state;
+ assert(state != NULL);
+
+ uint32_t mask;
+
+ intno &= 15;
+ mask = 1 << intno;
+
+ DPRINTF("grlib_irqmp_ack %d\n", intno);
+
+ /* Clear registers */
+ state->pending &= ~mask;
+ state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
+
+ grlib_irqmp_check_irqs(state);
+}
+
+void grlib_irqmp_set_irq(void *opaque, int irq, int level)
+{
+ assert(opaque != NULL);
+
+ IRQMP *irqmp = FROM_SYSBUS(typeof (*irqmp), sysbus_from_qdev(opaque));
+ assert(irqmp != NULL);
+
+ IRQMPState *s = irqmp->state;
+ assert(s != NULL);
+ assert(s->parent != NULL);
+
+ int i = 0;
+
+
+ if (level) {
+ DPRINTF("Raise CPU IRQ %d\n", irq);
+
+ if (s->broadcast & 1 << irq) {
+ /* Broadcasted IRQ */
+ for (i = 0; i < IRQMP_MAX_CPU; i++) {
+ s->force[i] |= 1 << irq;
+ }
+ } else {
+ s->pending |= 1 << irq;
+ }
+ grlib_irqmp_check_irqs(s);
+
+ }
+}
+
+static uint32_t grlib_irqmp_readl(void *opaque, target_phys_addr_t addr)
+{
+ IRQMP *irqmp = opaque;
+ assert(irqmp != NULL);
+
+ IRQMPState *state = irqmp->state;
+ assert(state != NULL);
+
+ addr &= 0xff;
+
+ /* global registers */
+ switch (addr)
+ {
+ case LEVEL_OFFSET:
+ return state->level;
+
+ case PENDING_OFFSET:
+ return state->pending;
+
+ case FORCE0_OFFSET:
+ /* This register is an "alias" for the force register of CPU 0 */
+ return state->force[0];
+
+ case CLEAR_OFFSET:
+ case MP_STATUS_OFFSET:
+ /* Always read as 0 */
+ return 0;
+
+ case BROADCAST_OFFSET:
+ return state->broadcast;
+
+ default:
+ break;
+ }
+
+ /* mask registers */
+ if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
+ int cpu = (addr - MASK_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ return state->mask[cpu];
+ }
+
+ /* force registers */
+ if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
+ int cpu = (addr - FORCE_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ return state->force[cpu];
+ }
+
+ /* extended (not supported) */
+ if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
+ int cpu = (addr - EXTENDED_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ return state->extended[cpu];
+ }
+
+ DPRINTF("read unknown register " TARGET_FMT_plx "\n", addr);
+ return 0;
+}
+
+static void
+grlib_irqmp_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
+{
+ IRQMP *irqmp = opaque;
+ assert(irqmp != NULL);
+
+ IRQMPState *state = irqmp->state;
+ assert(state != NULL);
+
+ addr &= 0xff;
+
+ /* global registers */
+ switch (addr)
+ {
+ case LEVEL_OFFSET:
+ value &= 0xFFFF << 1; /* clean up the value */
+ state->level = value;
+ return;
+
+ case PENDING_OFFSET:
+ /* Read Only */
+ return;
+
+ case FORCE0_OFFSET:
+ /* This register is an "alias" for the force register of CPU 0 */
+
+ value &= 0xFFFE; /* clean up the value */
+ state->force[0] = value;
+ grlib_irqmp_check_irqs(irqmp->state);
+ return;
+
+ case CLEAR_OFFSET:
+ value &= ~1; /* clean up the value */
+ state->pending &= ~value;
+ return;
+
+ case MP_STATUS_OFFSET:
+ /* Read Only (no SMP support) */
+ return;
+
+ case BROADCAST_OFFSET:
+ value &= 0xFFFE; /* clean up the value */
+ state->broadcast = value;
+ return;
+
+ default:
+ break;
+ }
+
+ /* mask registers */
+ if (addr >= MASK_OFFSET && addr < FORCE_OFFSET) {
+ int cpu = (addr - MASK_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ value &= ~1; /* clean up the value */
+ state->mask[cpu] = value;
+ grlib_irqmp_check_irqs(irqmp->state);
+ return;
+ }
+
+ /* force registers */
+ if (addr >= FORCE_OFFSET && addr < EXTENDED_OFFSET) {
+ int cpu = (addr - FORCE_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ uint32_t force = value & 0xFFFE;
+ uint32_t clear = (value >> 16) & 0xFFFE;
+ uint32_t old = state->force[cpu];
+
+ state->force[cpu] = (old | force) & ~clear;
+ grlib_irqmp_check_irqs(irqmp->state);
+ return;
+ }
+
+ /* extended (not supported) */
+ if (addr >= EXTENDED_OFFSET && addr < IRQMP_REG_SIZE) {
+ int cpu = (addr - EXTENDED_OFFSET) / 4;
+ assert(cpu >= 0 && cpu < IRQMP_MAX_CPU);
+
+ value &= 0xF; /* clean up the value */
+ state->extended[cpu] = value;
+ return;
+ }
+
+ DPRINTF("write unknown register " TARGET_FMT_plx "\n", addr);
+}
+
+static CPUReadMemoryFunc * const grlib_irqmp_read[] = {
+ NULL, NULL, &grlib_irqmp_readl,
+};
+
+static CPUWriteMemoryFunc * const grlib_irqmp_write[] = {
+ NULL, NULL, &grlib_irqmp_writel,
+};
+
+static void grlib_irqmp_reset(DeviceState *d)
+{
+ IRQMP *irqmp = container_of(d, IRQMP, busdev.qdev);
+ assert(irqmp != NULL);
+ assert(irqmp->state != NULL);
+
+ memset(irqmp->state, 0, sizeof *irqmp->state);
+ irqmp->state->parent = irqmp;
+}
+
+static int grlib_irqmp_init(SysBusDevice *dev)
+{
+ IRQMP *irqmp = FROM_SYSBUS(typeof (*irqmp), dev);
+ int irqmp_regs;
+
+ assert(irqmp != NULL);
+ assert(irqmp->env != NULL);
+
+ irqmp_regs = cpu_register_io_memory(grlib_irqmp_read,
+ grlib_irqmp_write,
+ irqmp);
+
+ irqmp->state = qemu_mallocz(sizeof *irqmp->state);
+
+ if (irqmp_regs < 0) {
+ return -1;
+ }
+
+ sysbus_init_mmio(dev, IRQMP_REG_SIZE, irqmp_regs);
+
+ return 0;
+}
+
+static SysBusDeviceInfo grlib_irqmp_info = {
+ .init = grlib_irqmp_init,
+ .qdev.name = "grlib,irqmp",
+ .qdev.reset = grlib_irqmp_reset,
+ .qdev.size = sizeof(IRQMP),
+ .qdev.props = (Property[]) {
+ {
+ .name = "cpustate",
+ .info = &qdev_prop_ptr,
+ .offset = offsetof(IRQMP, env),
+ .defval = (void*[]) { NULL },
+ },
+ {/* end of list */}
+ }
+};
+
+static void grlib_irqmp_register(void)
+{
+ sysbus_register_withprop(&grlib_irqmp_info);
+}
+
+device_init(grlib_irqmp_register)
--
1.7.1
- [Qemu-devel] [PATCH v2 0/6] [RFC] New SPARC machine: Leon3, Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 1/6] Emulation of GRLIB GPTimer as defined in GRLIB IP Core User's Manual., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 2/6] Emulation of GRLIB IRQMP as defined in GRLIB IP Core User's Manual.,
Fabien Chouteau <=
- [Qemu-devel] [PATCH v2 3/6] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 4/6] Header file for the GRLIB components., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Fabien Chouteau, 2011/01/03
- [Qemu-devel] [PATCH v2 6/6] SPARCV8 asr17 register support., Fabien Chouteau, 2011/01/03
- Re: [Qemu-devel] [PATCH v2 6/6] SPARCV8 asr17 register support., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Fabien Chouteau, 2011/01/17
- Re: [Qemu-devel] [PATCH v2 5/6] Emulation of Leon3., Blue Swirl, 2011/01/17
- Re: [Qemu-devel] [PATCH v2 4/6] Header file for the GRLIB components., Blue Swirl, 2011/01/04
- Re: [Qemu-devel] [PATCH v2 3/6] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual., Blue Swirl, 2011/01/04