[Qemu-devel] Re: [patch uq/master 7/8] MCE: Relay UCR MCE to guest

[Marcelo Tosatti]

On Wed, Oct 06, 2010 at 10:58:36AM +0900, Hidetoshi Seto wrote:
> I got some more question:
> 
> (2010/10/05 3:54), Marcelo Tosatti wrote:
> > Index: qemu/target-i386/cpu.h
> > ===================================================================
> > --- qemu.orig/target-i386/cpu.h
> > +++ qemu/target-i386/cpu.h
> > @@ -250,16 +250,32 @@
> >  #define PG_ERROR_RSVD_MASK 0x08
> >  #define PG_ERROR_I_D_MASK  0x10
> >  
> > -#define MCG_CTL_P  (1UL<<8)   /* MCG_CAP register available */
> > +#define MCG_CTL_P  (1ULL<<8)   /* MCG_CAP register available */
> > +#define MCG_SER_P  (1ULL<<24) /* MCA recovery/new status bits */
> >  
> > -#define MCE_CAP_DEF        MCG_CTL_P
> > +#define MCE_CAP_DEF        (MCG_CTL_P|MCG_SER_P)
> >  #define MCE_BANKS_DEF      10
> >  
> 
> It seems that current kvm doesn't support SER_P, so injecting SRAO
> to guest will mean that guest receives VAL|UC|!PCC and RIPV event
> from virtual processor that doesn't have SER_P.

Dean also noted this. I don't think it was deliberate choice to not
expose SER_P. Huang?

> I think most OSes don't expect that it can receives MCE with !PCC
> on traditional x86 processor without SER_P.
> 
> Q1: Is it safe to expect that guests can handle such !PCC event?
> Q2: What is the expected behavior on the guest?
> Q3: What happen if guest reboots itself in response to the MCE?
> 
> 
> Thanks,
> H.Seto