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[Qemu-devel] [PATCH 08/10] target-mips: add microMIPS exception handler
From: |
Nathan Froyd |
Subject: |
[Qemu-devel] [PATCH 08/10] target-mips: add microMIPS exception handler support |
Date: |
Thu, 20 May 2010 07:52:28 -0700 |
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers.
Signed-off-by: Nathan Froyd <address@hidden>
---
target-mips/helper.c | 21 +++++++++++++++------
1 files changed, 15 insertions(+), 6 deletions(-)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 8102f03..90c3b3a 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -385,6 +385,18 @@ static target_ulong exception_resume_pc (CPUState *env)
return bad_pc;
}
+static void set_hflags_for_handler (CPUState *env)
+{
+ /* Exception handlers are entered in 32-bit mode. */
+ env->hflags &= ~(MIPS_HFLAG_M16);
+ /* ...except that microMIPS lets you choose. */
+ if (env->insn_flags & ASE_MICROMIPS) {
+ env->hflags |= (!!(env->CP0_Config3
+ & (1 << CP0C3_ISA_ON_EXC))
+ << MIPS_HFLAG_M16_SHIFT);
+ }
+}
+
#endif
void do_interrupt (CPUState *env)
@@ -440,8 +452,7 @@ void do_interrupt (CPUState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
break;
case EXCP_RESET:
cpu_reset(env);
@@ -461,8 +472,7 @@ void do_interrupt (CPUState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
break;
case EXCP_EXT_INTERRUPT:
cause = 0;
@@ -581,8 +591,7 @@ void do_interrupt (CPUState *env)
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
env->active_tc.PC += offset;
- /* Exception handlers are entered in 32-bit mode. */
- env->hflags &= ~(MIPS_HFLAG_M16);
+ set_hflags_for_handler(env);
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause <<
CP0Ca_EC);
break;
default:
--
1.6.3.2
- [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 02/10] target-mips: add microMIPS-specific bits to mips-defs.h, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 01/10] target-mips: break out [ls][wd]c1 and rdhwr insn generation, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 05/10] target-mips: small changes to use new FMT_ enums, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 07/10] target-mips: add microMIPS CPUs, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 06/10] target-mips: add microMIPS ASE support, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 08/10] target-mips: add microMIPS exception handler support,
Nathan Froyd <=
- [Qemu-devel] [PATCH 03/10] target-mips: add enum constants for various invocations of FOP, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 04/10] target-mips: refactor {c, abs}.cond.fmt insns, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 10/10] hw: honor low bit in mipssim machine, Nathan Froyd, 2010/05/20
- [Qemu-devel] [PATCH 09/10] linux-user: honor low bit of entry PC for MIPS, Nathan Froyd, 2010/05/20